• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2001년도 하계 학술대회 논문집(KISPS SUMMER CONFERENCE 2001
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• pp.73-76
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• 2001

High-level synthesis(HLS)는 주어진 동작(behavior)과 면적(area), 성능(performance), 전력 소비량, 패키징, 테스팅등의 주어진 제한을 만족하게 구현된 구조적 디자인을 생성한다. 즉 high-level synthesis란 디지털 시스템의 알고리즘 단계 서술로부터 레지스터 전달구조의 구현에 이르는 과정을 의미한다. 이러한 high-level synthesis의 과정은 컴파일, 분할(partitioning), 스케줄링(scheduling)등의 단계를 거쳐 디지털 시스템을 설계할 수 있다. 본 논문에서는 high-level synthesis의 단계 중 스케줄링 과정에서 제한조건이 실리콘 면적으로 주어지는 경우에 최적의 functional unit의 수를 찾아내어 최소의 control step에 효과적으로 스케줄링 가능한 알고리즘을 제안하였다.

• Journal of Welding and Joining
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• 제31권4호
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• pp.17-22
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• 2013

The excellent beam quality of high power fiber lasers are commonly used for remote welding applications in body job applications. The Welding speed and productivity is unmatched with any other welding technology including resistance spot welding or traditional laser welding. High tooling cost for clamping and bulky safety enclosures are obstacles which are limiting the use. With the newly developed Laser stitch welding gun we have an integrated clamping in the process tool and the laser welding is shielded in a way that no external enclosure is needed. Operation of this laser welding gun is comparable with resistance spot welding but 2-times faster. Laser stitch welding is faster than spot welding and slower than remote welding. It is a laser welding tool with all the laser benefits like welding of short flanges, weld ability of Ultra High Strength steel, 3 layers welding and Aluminium welding. Together with low energy consumption and minimum operation cost of IPG fiber laser it is a new and sharp tool for economic car body assembly.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.31-34
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• 2009

We investigated the effect of relative dielectric constant of front dielectric layer on the efficacy of plasma display panel. Dielectric materials with relative dielectric constant of around 6 and 7 were developed. When the front dielectric layer had a low relative dielectric constant, power consumption decreased more than luminance did. And it led to efficacy enhancement. However, the minimum sustain voltage increased.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회B
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• pp.2256-2261
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• 2008

The electric snow melting and deicing system by electric heating cable which is adopted in this study is a part of road facilities to keep surface temperature of the road higher than freezing point of water for melting the snow or ice accumulated on it. The electric heating cables are buried under paved road at a certain depth and a certain pitch and operated automatically and manually. Design theory, amount of heating, and installation standard vary according to economic situation, weather condition, and installation place. A main purpose of this study is figuring out the appropriate range of required heat capacity and installation depth and pitches for solving snowdrifts and freezing problems with minimum electric power consumption. This study was performed under the ambient air temperature($-2^{\circ}C$, $-5^{\circ}C$), the pitches of the electric heating cables (200 mm, 300 mm), heating value ($250\;W/m^2$, $300\;W/m^2$, $350\;W/m^2$).

• ETRI Journal
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• 제43권6호
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• pp.1113-1129
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• 2021

Lightweight ciphers are increasingly employed in cryptography because of the high demand for secure data transmission in wireless sensor network, embedded devices, and Internet of Things. The PRESENT algorithm as an ultralightweight block cipher provides better solution for secure hardware cryptography with low power consumption and minimum resource. This study generates the key using key rotation and substitution method, which contains key rotation, key switching, and binary-coded decimal-based key generation used in image encryption. The key rotation and substitution-based PRESENT architecture is proposed to increase security level for data stream and randomness in cipher through providing high resistance to attacks. Lookup table is used to design the key scheduling module, thus reducing the area of architecture. Field-programmable gate array (FPGA) performances are evaluated for the proposed and conventional methods. In Virtex 6 device, the proposed key rotation and substitution PRESENT architecture occupied 72 lookup tables, 65 flip flops, and 35 slices which are comparably less to the existing architecture.

• ETRI Journal
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• 제45권3호
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• pp.433-447
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• 2023

Critical issues such as connection congestion, long transmission delay, and packet loss become even worse during epidemic, disaster, and so on. In this study, a link load balancing method is proposed to address these issues on the data plane, a plane of the software-defined network (SDN) architecture. These problems are NP-complete, so a meta-heuristic approach, discrete particle swarm optimization, is used with a novel hybrid cost function. The superiority of the proposed method over existing methods in the literature is that it provides link and switch load balancing simultaneously. The goal is to choose a path that minimizes the connection load between the source and destination in multipath SDNs. Furthermore, the proposed work is dynamic, so selected paths are regularly updated. Simulation results prove that with the proposed method, streams reach the target with minimum time, no loss, low power consumption, and low memory usage.

• 한국정보통신학회논문지
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• 제20권12호
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• pp.2219-2225
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• 2016

이동통신망에서는 채널 사용을 극대화하기 위하여 제한된 송신 전력으로 멀티미디어 트래픽을 지원해야 한다. 실시간 전송 기반의 데이터들은 지연에 민감하므로 이를 고려해야 하고, 비실시간성 데이터는 비교적 지연에 둔감하므로 패킷 손실에 유연하게 대처할 수 있다. 따라서 제한된 송신 전력으로 멀티미디어 트래픽을 지원하여야 하므로 하향 링크 전력을 최소로 유지하면서 QoE 제약 조건을 충족시키는 방안이 필요하다. 전송률의 증가에 따라 소비되는 전력이 크게 증대되므로 다양한 이동 멀티미디어 서비스를 지원하기 위해서는 에너지 소비 절감 기술이 요구된다. 또한 인터넷 기반의 멀티미디어 서비스는 자원 요구량, QoE 요건이 상이하므로 적응적인 전력 관리가 필수적이다. 따라서 본 논문에서는 QoE을 일정 수준으로 충족시키면서 전력 소모를 최소화하기 위한 방안을 제안한다.

• 한국ITS학회 논문지
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• 제11권2호
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• pp.92-101
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• 2012

이 논문에서는 무선 멀티홉 네트워크 환경에서 종단간 최적 전송률을 제공하기 위한 분산 송신전력제어 방안을 제안한다. 제안 방안은 멀티홉 구성 링크들의 전송률이 갖는 연대 특성과 멀티홉 종단간 전송률이 최소 링크 전송률에 의해 결정된다는 점을 고려하여, 멀티홉 구성 링크들의 전송률이 모두 같아지도록 송신전력을 제어함으로써 종단간 전송률을 최대화 한다. 또한 제안 방안은 이웃단말과의 정보 공유만을 가지고 단말 스스로 송신전력 값을 계산하는 분산 방식으로 송신전력 제어에 필요한 정보 교환 오버헤드를 줄인다. 시뮬레이션 결과 제안 방안은 고정된 최대 송신전력 값을 사용한 기존 방식 대비 종단간 전송률과 전력소비 측면에서 큰 성능이득을 보여준다.

• International journal of advanced smart convergence
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• 제11권4호
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• pp.96-103
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• 2022

This paper presents the analysis of increasing the resolution of True-Time-Delay (TTD) by 0.5-bit for phased-array antenna system which is one of the Multiple-Input and Multiple Output (MIMO) technologies. For the analysis, a 5.5-bit True-Time Delay (TTD) integrated circuit is designed and analyzed in terms of beam steering performance. In order to increase the number of effective bits, the designed 5.5-bit TTD uses Single Pole Triple Throw (SP3T) and Double Pole Triple Throw (DP3T) switches, and this method can minimize the circuit area by inserting the minimum time delay of 0.5-bit. Furthermore, the circuit mostly maintains the performance of the circuit with the fully added bits. The idea of adding 0.5-bit is verified by analyzing the relation between the number of bits and array elements. The 5.5-bit TTD is designed using 0.18 ㎛ RF CMOS process and the estimated size of the designed circuit excluding the pad is 0.57×1.53 mm². In contrast to the conventional phase shifter which has distortion of scanning angle known as beam squint phenomenon, the proposed TTD circuit has constant time delays for all states across a wide frequency range of 4 - 20 GHz with minimized power consumption. The minimum time delay is designed to have 1.1 ps and 2.2 ps for the 0.5-bit option and the normal 1-bit option, respectively. A simulation for beam patterns where the 10 phased-array antenna is assumed at 10 GHz confirms that the 0.5-bit concept suppresses the pointing error and the relative power error by up to 1.5 degrees and 80 mW, respectively, compared to the conventional 5-bit TTD circuit.

• 한국정보통신학회논문지
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• 제17권2호
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• pp.378-384
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• 2013

본 논문에서는 칩 내부의 온도를 측정하기 위한 CMOS 온도 센서가 제안된다. 제안하는 온도 센서는 칩 내부의 온도에 비례하는 전압을 생성하는 proportional-to-absolute-temperature (PTAT) 회로와 디지털 인터페이스를 위한 4-비트 아날로그-디지털 변환기로 구성된다. 소면적을 가지는 PTAT 회로는 CMOS 공정에서 vertical PNP 구조를 이용하여 설계된다. 온도변화에 둔감한 저전력 4-비트 아날로그-디지털 변환기를 구현하기 위해 아날로그 회로를 최소로 사용하는 축차근사형 아날로그-디지털 변환기가 이용되며, 이를 위해 커패시터-기반 디지털-아날로그 변환기와 시간-도메인 비교기를 이용한다. 제안된 온도 센서는 2.5V $0.25{\mu}m$ 1-poly 6-metal CMOS 공정에서 제작되었고, $50{\sim}150^{\circ}C$ 온도 범위에서 동작한다. 구현된 온도 센서의 면적과 전력 소모는 각각 $130{\times}390{\mu}m^2$과 $868{\mu}W$이다.