• Korean Journal of Materials Research
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• v.20 no.8
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• pp.423-428
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• 2010

This study shows the effects of deionized (DI) rinse and oxide HF wet etch processes on silicon substrate during a photolithography process. We found a fail at the wafer center after DI rinse step, called Si pits, during the fabrication of a complementary metal-oxide-semiconductor (CMOS) device. We tried to find out the mechanism of the Si pits by using the silicon wafer on CMOS fabrication and analyzing the effects of the friction charge induced by the DI rinsing. The key parameters of this experiment were revolution per minute (rpm) and time. An incubation time of above 10 sec was observed for the formation of Si pits and the rinsing time was more effective than rpm on the formation of the Si pits. The formation mechanism of the Si pits and optimized rinsing process parameters were investigated by measuring the charging level using a plasma density monitor. The DI rinse could affect the oxide substrate by a friction charging phenomenon on the photolithography process. Si pits were found to be formed on the micro structural defective site on the Si substrate under acceleration by developed and accumulated charges during DI rinsing. The optimum process conditions of DI rinse time and rpm could be established through a systematic study of various rinsing conditions.

• 전자공학회논문지 IE
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• v.48 no.2
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• pp.6-11
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• 2011

This paper describes the design of new method of propagation delay measurement in micro and nanostructures during characterization of ASIC standard library cell. Providing more accuracy timing information about library cell (NOR, AND, XOR, etc.) to the design team we can improve a quality of timing analysis inside of ASIC design flow process. Also, this information could be very useful for semiconductor foundry team to make correction in technology process. By comparison of the propagation delay in the CMOS element and result of analog SPICE simulation, we can make assumptions about accuracy and quality of the transistor's parameters. Physical implementation of phase error accumulation method(PHEAM) can be easy integrated at the same chip as close as possible to the device under test(DUT). It was implemented as digital IP core for semiconductor manufacturing process($0.11{\mu}m$, GL130SB). Specialized method helps to observe the propagation time delay in one element of the standard-cell library with up-to picoseconds accuracy and less. Thus, the special useful solutions for VLSI schematic-to-parameters extraction (STPE), basic cell layout verification, design simulation and verification are announced.

• Journal of IKEEE
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• v.24 no.1
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• pp.200-207
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• 2020

In this paper, an area-efficient feature extractor was proposed for security surveillance radar systems and FPGA-based implementation results were presented. In order to reduce the memory requirements, features extracted from Doppler profile for FFT window-size are used, while those extracted from total spectrogram for frame-size are excluded. The proposed feature extractor was design using Verilog-HDL and implemented with Xilinx Zynq-7000 FPGA device. Implementation results show that the proposed design can reduce the logic slice and memory requirements by 58.3% and 98.3%, respectively, compared with the existing research. In addition, security surveillance radar system with the proposed feature extractor was implemented and experiments to classify car, bicycle, human and kickboard were performed. It is confirmed from these experiments that the accuracy of classification is 93.4%.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.1
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• pp.34-42
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• 2001

A battery is the device that transforms the chemical energy into the direct-current electrical energy directly without a mechanical process. Unit cells are connected in series to obtain the required voltage, while being connected in parallel to organize capacity for load current and to decrease the internal resistance for corresponding the sudden shift of the load current. Because the voltage droop down in one set of battery is faster than in tow one, it amy result in the low efficiency of power converter with the voltage drop and cause the system shutdown. However, when the system being driven in parallel, a circular-current can be generated. The changing current differs in each set of battery because the system including batteries, rectifiers and loads is connected in parallel and it makes the charge voltage constant. It is shown that, as a result the new batteries are heated by over-charge and over-discharge, and the over charge current increases rust of the positive grid and consequently shortens the lifetime of the new batteries. The difference between the new batteries and old ones is the amount of internal resistance. In this paper, we can detect the unbalance current using the micro-processor and achieve the balance current by adjusting resistance of each set. The internal resistance of each set becomes constant and the current of charge and discharge comes to be balanced by inserting the external resistance into the system and calculating the change of internal resistance.

• The KIPS Transactions:PartD
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• v.8D no.3
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• pp.265-272
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• 2001

In case of implementing a complicated application like WAP (Wireless Application Protocol) in a mobile terminal with the characteristics of bare machine and versatile kernel aspects of which are control, interrupt and IPC(Inter Process Communication), a special methodology should be needed. If not, it will cause more cost and human resources, even delayed product into launching for the time-to-market. This paper suggests AKL, (Abstract Kernel Layer) for the design and implementation of WAP on basis of multi-platform. AKL is running on the various kernel including REX, MS-DOS, MS-Window, UNIX and LINUX. For the purpose of it, AKL makes machine-dependant features be minimized and supports a consistent interface on API (Application Program Interface) point of view. Therefore, it makes poring times of a device be shorten and makes easy of maintenance. We validated our suggestion as a consequent of porting WAP into PlamV PDA and mobile phone with AKL.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.34 no.11
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• pp.1765-1771
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• 2010

In the case of micro.electro-mechanical system (MEMS) devices, the quality of punched via hole is one of the most important factors governing the performance of the device. The common features that affect the laser micromachining of via holes drilled by using Nd:$YVO_4$ laser are described, and efficient optimization methods to measure them are presented. The analysis methods involving an orthogonal array, analysis of variance (ANOVA), and response surface optimization are employed to determine the main effects and to determine the optimal laser process parameters. The significant laser process parameters were identified and their effects on the quality of via holes were studied. Finally, an experiment in which the optimal levels of the laser process parameters were used was carried out to demonstrate the effectiveness of the optimization method.

• The Journal of Korean Academic Society of Nursing Education
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• v.12 no.2
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• pp.265-271
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• 2006

Purpose: To analyze the newly developed vacuum assisted auto-lancing technique applied to the forearm for the purpose of obtaining an adequate blood sample for glucose test with minimal pain. Methods: Visual and facial pain measures were introduced to compare lancing pain between the forearm and fingertip in 58 normal females. Sampled blood volumes were accurately measured by computer scanning technique. Results: Visual pain measure demonstrated significant pain reduction effect of the forearm sampling compared with the traditional fingertip sampling, which was also consistent with facial pain measure results. Blood volume more than $0.5{\mu}L$, enough for blood glucose testing with modern glucometers, was collected in 399(86%) of 464 forearm samples. Conclusions: Capillary blood sampling could be performed with minimal pain on the forearm by the newly developed vacuum assisted auto-lancing technique. With some resampling when necessary, the forearm sampling seemed very useful, considering almost no pain felt by the patients.

• Journal of the Korean Vacuum Society
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• v.19 no.2
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• pp.141-147
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• 2010

In this study, high-k oxide films like $Al_2O_3$, $TiO_2$, $HfO_2$ were deposited on Si, $SiO_2$/Si, GaAs wafers, and then the thermal conductivity was measured by using thermo-reflectance method which utilizes the reflectance variation of the film surface produced by the periodic temperature variation. The result shows that high-k oxide films with 50 nm thickness have high thermal conductivity of 0.80~1.29 W/(mK). Therefore, effectively dissipate the heat generated in the electric circuit such as CMOS memory device, and the heat transfer changes according to the micro grain size.

• Journal of Ocean Engineering and Technology
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• v.26 no.5
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• pp.63-72
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• 2012

The product lifecycle of a marine vessel can be classified into the design-production, operation-maintenance, and disposal phases. During the operation and maintenance phase, status data should be gathered from the major machinery and instruments installed on the marine vessel in order to perform efficient maintenance work. Although a PLM (product lifecycle management) system can manage the product information during the design and assembly stage, a PLM based on asset management technology is more appropriate for product information management during the operation stage. Product embedded information devices (PEIDs) are suggested for gathering real-time maintenance information during the operation and maintenance lifecycle. A PEID allows PLM to provide the capability of offering active information exchange between the lifecycle management system and equipment. This study designed a PEID to effectively obtain information and interact with a PLM system. It consists of sensors, wireless communication, and a micro-processor, which allow it to accumulate status data on the PLM system. The embedded information device and PLM enable the seamless information flow, tracking, and updating of MRO (maintenance repair and overhaul) information for a product throughout the middle of the product lifecycle.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.2
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• pp.829-834
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• 2011

Exposure process is the most important technology to fabricate highly integrated circuit. Up to now, mask type lithography process has been generally used. However, it is not efficient for small quantity and/or frequently changing products. Therefore, maskless lithography technology is raised in exposure process. In this study, relations between multi-beam energy and overlay were analyzed. Exposure experiment of generating pattern was performed. It was from presented scan line by multi- beam simulation. As a result, optimal scan line distance was proposed by simulation, and micro pattern accuracy could be improved by exposure experiment using laser direct imaging system.