• 제목/요약/키워드: metal oxide semiconductor

검색결과 713건 처리시간 0.025초

$2{\mu}m$ CMOS P-WELL DOUBLE METAL TECHNOLOGY

  • 신철호;안경호;정은승;진주현
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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    • pp.424-428
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    • 1987
  • A $2{\mu}m$ CMOS P-well double metal technology has been developed. Phosphorus deep implantation and drive-in diffusion steps were utilized to prevent the low voltage bulk punch through in the short channel, 1.6[${\mu}m$] Leff, PMOS device. Double metal process with the rules of 5[${\mu}m$] 1st metal pitch and 7[${\mu}m$] 2nd metal pitch was successfully implemented by using VLTO, low temperature oxide, as on intermetal dielectric.

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플라즈마 에칭으로 손상된 4H-실리콘 카바이드 기판위에 제작된 MOS 커패시터의 전기적 특성 (Electrical Characterization of MOS (metal-oxide-semiconductor) Capacitors on Plasma Etch-damaged 4H-Silicon Carbide)

  • 조남규;구상모;우용득;이상권
    • 한국전기전자재료학회논문지
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    • 제17권4호
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    • pp.373-377
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    • 2004
  • We have investigated the electrical characterization of metal-oxide-semiconductor (MOS) capacitors formed on the inductively coupled plasma (ICP) etch-damaged both n- and p-type 4H-SiC. We found that there was an effect of a sacrificial oxidation treatment on the etch-damaged surfaces. Current-voltage and capacitance-voltage measurements of these MOS capacitors were used and referenced to those of prepared control samples without etch damage. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged 4H-SiC since the effective interface density and fixed oxide charges of etch-damaged samples have been found to increase while the breakdown field strength of the oxide decreased and the barrier height at the SiC-SiO$_2$ interface decreased for MOS capacitors on etch-damaged surfaces.

Effect of Dopants on Cobalt Silicidation Behavior at Metal-oxide-semiconductor Field-effect Transistor Sidewall Spacer Edge

  • Kim, Jong-Chae;Kim, Yeong-Cheol;Kim, Byung-Kook
    • 한국세라믹학회지
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    • 제38권10호
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    • pp.871-875
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    • 2001
  • Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

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Human body model electrostatic discharge tester using metal oxide semiconductor-controlled thyristors

  • Dong Yun Jung;Kun Sik Park;Sang In Kim;Sungkyu Kwon;Doo Hyung Cho;Hyun Gyu Jang;Jongil Won;Jong-Won Lim
    • ETRI Journal
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    • 제45권3호
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    • pp.543-550
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    • 2023
  • Electrostatic discharge (ESD) testing for human body model tests is an essential part of the reliability evaluation of electronic/electrical devices and components. However, global environmental concerns have called for the need to replace the mercury-wetted relay switches, which have been used in ESD testers. Therefore, herein, we propose an ESD tester using metal oxide semiconductor-controlled thyristor (MCT) devices with a significantly higher rising rate of anode current (di/dt) characteristics. These MCTs, which have a breakdown voltage beyond 3000 V, were developed through an in-house foundry. As a replacement for the existing mercury relays, the proposed ESD tester with the developed MCT satisfies all the requirements stipulated in the JS-001 standard for conditions at or below 2000 V. Moreover, unlike traditional relays, the proposed ESD tester does not generate resonance; therefore, no additional circuitry is required for resonant removal. To the best of our knowledge, the proposed ESD tester is the first study to meet the JS-001 specification by applying a new switch instead of an existing mercury-wetted relay.

Analysis Method of Volatile Sulfur Compounds Utilizing Separation Column and Metal Oxide Semiconductor Gas Sensor

  • Han-Soo Kim;Inho Kim;Eun Duck Park;Sang-Do Han
    • 센서학회지
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    • 제33권3호
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    • pp.125-133
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    • 2024
  • Gas chromatography (GC) separation technology and metal oxide semiconductor (MOS) gas sensors have been integrated for the effective analysis of volatile sulfur compounds (VSCs) such as H2S, CH3SH, (CH3)2S, and (CH3)2S2. The separation and detection characteristics of the GC/MOS system using diluted standard gases were investigated for the qualitative and quantitative analysis of VSCs. The typical concentrations of the standard gases were 0.1, 0.5, 1.0, 5.0, and 10.0 ppm. The GC/MOS system successfully separated H2S, CH3SH, (CH3)2S, and (CH3)2S2 using a celite-filled column. The reproducibility of the retention time measurements was at a 3% relative standard deviation level, and the correlation coefficient (R2) for the VSC concentration was greater than 0.99. In addition, the chromatograms of single and mixed gases were almost identical.

Solution-processed indium-zinc oxide with carrier-suppressing additives

  • Kim, Dong Lim;Jeong, Woong Hee;Kim, Gun Hee;Kim, Hyun Jae
    • Journal of Information Display
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    • 제13권3호
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    • pp.113-118
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    • 2012
  • Metal oxide semiconductors were considered promising materials as backplanes of future displays. Moreover, the adoption of carrier-suppressing metal into indium-zinc oxide (IZO) has become one of the most important themes in the metal oxide research field. In this paper, efforts to realize and optimize IZO with diverse types of carrier suppressors are summarized. Properties such as the band gap of metal in the oxidized form and its electronegativity were examined to confirm their relationship with the metal's carrier-suppressing ability. It was concluded that those two properties could be used as indicators of the carrier-suppressing ability of a material. As predicted by the properties, the alkali earth metals and early transition metals used in the research effectively suppressed the carrier and optimized the electrical properties of the metal oxide semiconductors. With the carrier-suppressing metals, IZO-based thin-film transistors with high (above $1cm^2/V{\cdot}s$) mobility, a lower than 0.6V/dec sub-threshold gate swing, and an over $3{\times}10^6$ on-to-off current ratio could be achieved.

Design of Metal Oxide Hollow Structures Using Soft-templating Method for High-Performance Gas Sensors

  • Shim, Young-Seok;Jang, Ho Won
    • 센서학회지
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    • 제25권3호
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    • pp.178-183
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    • 2016
  • Semiconductor gas sensors based on metal oxide are widely used in a number of applications, from health and safety to energy efficiency and emission control. Nanomaterials including nanowires, nanorods, and nanoparticles have dominated the research focus in this field owing to their large number of surface sites that facilitate surface reactions. Recently, metal oxide hollow structures using soft templates have been developed owing to their high sensing properties with large-area uniformity. Here, we provide a brief overview of metal oxide hollow structures and their gas-sensing properties from the aspects of template size, morphology, and additives. In addition, a gas-sensing mechanism and perspectives are presented.

작동중인 모스 전계 효과 트랜지스터 단면에서의 상대온도 및 전위 분포 측정 (Cross Sectional Thermal and Electric Potential Imaging of an Operating MOSFET)

  • 권오명
    • 대한기계학회논문집B
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    • 제27권7호
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    • pp.829-836
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    • 2003
  • Understanding of heat generation in semiconductor devices is important in the thermal management of integrated circuits and in the analysis of the device physics. Scanning thermal microscope was used to measure the temperature and the electric potential distribution on the cross-section of an operating metal-oxide-semiconductor field-effect transistor (MOSFET). The temperature distributions were measured both in DC and AC modes in order to take account of the leakage current. The measurement results showed that as the drain bias was increased the hot spot moved to the drain. The density of the iso-potential lines near the drain increased with the increase in the drain bias.

마이크로 칩의 정전기 방지를 위한 DPS-GG-EDNMOS 소자의 특성 (Characteristics of Double Polarity Source-Grounded Gate-Extended Drain NMOS Device for Electro-Static Discharge Protection of High Voltage Operating Microchip)

  • 서용진;김길호;이우선
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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    • pp.97-98
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    • 2006
  • High current behaviors of the grounded gate extended drain N-type metal-oxide-semiconductor field effects transistor (GG_EDNMOS) electro-static discharge (ESD) protection devices are analyzed. Simulation based contour analyses reveal that combination of BJT operation and deep electron channeling induced by high electron injection gives rise to the 2-nd on-state. Thus, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

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기판 막질에 따른 $TEOS-O_3$ 산화막의 증착 특성 (Deposition Characteristics of $TEOS-O_3$ Oxide Film on Substrate)

  • 안용철;박인선;최지현;정우인;이정규;이종길
    • 한국재료학회지
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    • 제2권1호
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    • pp.76-82
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    • 1992
  • $TEOS-O_3$ 산화막은 깔개층 물질에 따라 증착속도가 변하는 특성을 나타낸다. 본 논문에서는 $TEOS-O_3$ 산화막의 깔개층 물질 의존성 이외에도 배선 밀도, 배선 간격에 따라 증착속도가 달라지는 패턴 의존성에 대하여 조사하였다. 또한 $TEOS-O_3$ 산화막의 깔개층 물질 의존성 및 패턴 의존성을 줄이기 위해 다층 배선에서 1차 배선후에 깔개층, 즉 TEOS-base 프라즈마 산화막 및 $SiH_4-base$ 프라즈마 산화막을 증착했을 때 $TEOS-O_3$ 산화막의 증착 특성을 조사하였다. 그리고 그 깔개층 물질에 $N_2$ 프라즈마 처리를 했을 때 $TEOS-O_3$ 산화막의 증착 특성에 대해 조사하였다. 그 결과 $TEOS-O_3$ 산화막에서 기판 위에 배선 밀도와 배선 간격에 따른 의존성은 깔개층물질이 $SiH_4-base$ 일때보다 TEOS-base 프라즈마 산화막인 경우 $N_2$ 프라즈마 처리를 하면 깔개층 물질 표면이 O-Si-N화 되므로써 의존성이 사라지게 된다.

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