• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.8
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• pp.1448-1455
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• 2008

This paper designs Shared Memory on the Dual Core system so that it operates a general System V IPC on the Linux O.S. Shared Memory is the technique that many processes can access to identical memory area. We treat Shared Memory in this paper among big two branches of Shared Memory which are SVR in a kernel step format. We design a share memory facility of Linux operating system on the Dual Core System. In this paper the suggesting design plan of share memory facility in Dual Core system is enhancing the performance in existing unity processor system as a dual core practical use. We attempt a performance enhance in each CPU for each process which uses a share memory.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.18 no.1
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• pp.44-51
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• 2004

Fractal-space multiplexing using a moving window(MW) can multiplex holograms by moving a window left and right. and up and down. But, crosstalk occurs by two neighboring moving windows in the vertical direction of the holographic memory system and limits high-density information recording. Accordingly, we analyzed the crosstalk with the focal length of lens, the distance of MW, and the number of multiplexed hologram to record high-density infromation and presented the optical experimental results of fractal-space multiplexing using volumetric photorefractive crystal and disc type photopolymer.

• International Journal of Aeronautical and Space Sciences
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• v.7 no.1
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• pp.91-98
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• 2006

The thermomechanical behaviors of SMA thin film actuator and their application are investigated. The numerical algorithm of the 2-D SMA thermomechanical constitutive equation is developed and implemented into the ABAQUS finite element program by using the user defined material (UMAT) subroutine. To verify the numerical algorithm of SMAs, the results are compared with experimental data. For the application of SMA thin film actuator, the methodology to maintain the precise configuration of inflatable membrane structure is demonstrated.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1995.10b
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• pp.264-272
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• 1995

This paper presents an efficient design method to realize an associative memory with BSB neural networks by means of the parametrization of the solution space and searching for the optimal solution using an evolution program. In particular, the performance index based on DOA analysis in this paper may make and associative memory implementation to reach on the level of practical success.

• International Journal of Aeronautical and Space Sciences
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• v.7 no.1
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• pp.137-147
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• 2006

In this study, shape memory alloy damper with characteristics of pseudoelastic hysteresis for helicopter rotor blades are investigated. SMAs can be available in damping augmentation of vibrating structures. SMAs show large hysteresis in the process of pseudoelastic austenite-martensite phase transformation which takes place while subjected to loading above the austenite finish temperature. Since SMAs display pseudoelastic hysteresis behavior over large strain ranges, a significant amount of energy dissipation is possible. A damper can be designed with SMA wires prestressed to a baseline level somewhere in the middle of the pseudoelastic stress range. An experimental study of the effects of pre-strain and cyclic strain amplitude as well as frequency on the damping behavior of pseudoelastic shape memory alloy wires are performed. The effects of the shape memory alloy damper on aeroelastic and ground resonance stability of helicopter are studied. In aeroelastic stability, the dynamic characteristics of blades related to pitch angle and the amplitude of lag motion for the rotor equipped with SMA damper were examined. The performance of SMA damper on ground resonance instability are presented through the frequencies and modal damping with respect to rotating speed.

• Journal of Information Processing Systems
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• v.17 no.1
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• pp.191-202
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• 2021

In an Internet of Things (IoT)-configured system, each device executes on-chip software. Recent IoT devices require fast execution time of complex services, such as analyzing a large amount of data, while maintaining low-power computation. As service complexity increases, the service requires high-performance computing and more space for embedded space. However, the low performance of IoT edge devices and their small memory size can hinder the complex and diverse operations of IoT services. In this paper, we propose a remote on-demand software code execution unit using the cloudification of on-chip code memory to accelerate the program execution of an IoT edge device with a low-performance processor. We propose a simulation approach to distribute remote code executed on the server side and on the edge side according to the program's computational and communicational needs. Our on-demand remote code execution unit simulation platform, which includes an instruction set simulator based on 16-bit ARM Thumb instruction set architecture, successfully emulates the architectural behavior of on-chip flash memory, enabling embedded devices to accelerate and execute software using remote execution code in the IoT environment.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.35-41
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• 2008

When memory devices are exposed to a space environment. they suffer various effects such as SEU(Single Event Upset). For these reasons, memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, the error detection and correction strategy in the Mass Memory Unit(MMU) of the STSAT-3 is discussed. The probability equation of un-recoverable SEUs in the mass memory system is derived when the whole memory is encoded and decoded by the RS(10,8) Reed-Solomon code. Also the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. The analyzed results can be used to determine the period of scrubbing the whole memory, which is one of the important parameters in the design of the MMU.

• Journal of Information Technology Applications and Management
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• v.11 no.1
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• pp.189-200
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• 2004

Recently Flash Memory which is small and low-powered is widely used as a storage of embedded system, because an embedded system requests portability and a fast response. To resolve a difference of access time between a storage and RAM, Linux is using disk caching which copies a part of file on disk into RAM. It is not also an exception on embedded system. A READ access-time of flash memory is similar to RAMs. So, when a process on an embedded system reads data, it is similar to the time to access cached data in RAM and to access directly data on a flash memory. On the embedded system using limited memory, using a disk cache is that wastes much time and memory spaces to manage it and can not reflects the characteristic of a flash memory. This paper proposes the regular file access of limited using a page cache in the file system based on a flash memory and reflects the characteristic of a flash memory. The proposed algorithm minimizes power consumption because access numbers of the RAM are reduced and doesn't waste a memory space because it accesses directly to a flash memory Therefore, the performance improvement of the system applying the proposed algorithm is expected.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.3
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• pp.161-171
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• 2010

As embedded systems adopt monolithic kernels, NAND flash memory is used for swap space of virtual memory systems. While flash memory has the advantages of low-power consumption, shock-resistance and non-volatility, it requires garbage collections due to its erase-before-write characteristic. The efficiency of garbage collection scheme largely affects the performance of flash memory. This paper proposes a novel garbage collection technique which exploits data redundancy between the main memory and flash memory in flash memory-based virtual memory systems. The proposed scheme takes the locality of data into consideration to minimize the garbage collection overhead. Experimental results demonstrate that the proposed garbage collection scheme improves performance by 37% on average compared to previous schemes.

• Korean Institute of Interior Design Journal
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• v.20 no.1
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• pp.138-145
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• 2011

This study analyzed the time to understand the space and the contents of information to be memorized in the indoor space. Understanding the space and examining the memory will not only provide the basic data on which visual activities occur in user's perceiving the designed space but also expand the activity range of interior designer. The summary of the study results is as follows: First, with respect to gender difference, the results showed that males grasped the space in a relatively shorter time. Females showed more concentrated distribution range than males. Second, as for the proper time by accumulative sum across time, the results showed that it increased continuously until V time zone(120~150 seconds), it decreased rapidly after the V zone, which indicated that the proper gazing time for the indoor space as the target of this study is less than 150 seconds(effective gazing time). Third, in terms of efficiency of information acquisition, the results suggested that "60~90 seconds" are the effective time for acquiring the greatest amount of information. Fourth, regarding the information acquisition method, males were approximately 4.1%~0.1% lower in the evaluation through phrase and image. The evaluation of subjects through phrase than image was connected to more accurate information acquisition.