• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.111-121
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• 2012

In this paper, a poly-Si thin film transistor with ${\sim}0.5{\mu}m$ gate length was fabricated and its electrical characteristics are optimized. From the results, it was verified that making active region with larger grain size using low temperature annealing is an efficient way to enhance the subthreshold swing, drain-induced barrier lowering and on-current characteristics. A SONOS flash memory was fabricated using this poly-Si channel process and its performances are analyzed. It was necessary to optimize O/N/O thickness for the reduction of electron back tunneling and the enhancement of its memory operation. The optimized device showed 2.24 V of threshold voltage memory windows which coincided with a well operating flash memory.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.34-40
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• 2010

This paper proposes an efficient CABAC encoder to reduce syntax element storage in H.264/AVC entropy coding. In the proposed architecture, all blocks are designed in dedicated hardware, so it performs fast processing without programmable processors. Context modeler of CABAC encoder requires the neighbor block data. However it requires impractically huge memory size if the neighbor block data is directly stored without proper processing. Therefore, this paper proposes an effective method of storing the neighbor block data to decrease memory size. The proposed CABAC encoder has 35,463 gates in 0.18um standard cell library. It operates at maximum speed of 180MHz and its throughput is about 1 cycle per input symbol.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.59-62
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• 1996

Plasma displays (PDP) as a large area wall-hanging display device are rabidly developed with flat CRT, TPT LCD and etc. Especially, AC Plasma Display Panels(AC PDPs) have the inherent memory function which is effective for large area displays. The memory function in AC PDPs is caused by the accumulation of the electrical charge on the protecting layer formed on the dielectric layer. This MgO protective layer prevents the dielectric layer from sputtering by ion in discharge plasma and also has the additional important roll in lowering the firing voltage due to the large secondary electron emission coefficient). Until now, the MgO Protective layer is mainly formed by E-Beam evaporation. With increasing the panel size, this process is difficult to attain cost reduction, and are not suitable for large quantity of production. To the contrary, the methode of shuttering are easy to apply on mass production and to enlarge the size of the panel and shows the superior adhesion and uniformity of thin film. In this study, we have prepared MgO protective layer on AC PDP Cell by reactive magnetron sputtering and studied the effect of MgO layer on the surface discharge characteristics of ac PDP.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.31-40
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• 2010

This paper describes a LDPC decoder for IEEE 802.11n wireless LAN standard. The designed processor supports parity check matrix for block length of 1,944 and code rate of 1/2 in IEEE 802.11n standard. To reduce hardware complexity, the min-sum algorithm and layered decoding architecture are adopted. A novel memory reduction technique suitable for min-sum algorithm was devised, and our design reduces memory size to 25% of conventional method. The LDPC decoder processor synthesized with a $0.35-{\mu}m$ CMOS cell library has 200,400 gates and memory of 19,400 bits, and the estimated throughput is about 135 Mbps at 80 MHz@2.5v. The designed processor is verified by FPGA implementation and BER evaluation to validate the usefulness as a LDPC decoder.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.2A
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• pp.209-215
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• 2010

This paper describes a design of variable-length FFT/IFFT processor (VL_FCore) for OFDM-based multi-standard communication systems. The VL_FCore adopts in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate various FFT lengths in the range of $N=64{\times}2^k\;(0{\leq}k{\leq}7)$. To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The VL_FCore synthesized with a $0.35-{\mu}m$ CMOS cell library has 23,000 gates and 32 Kbytes memory, and it can operate with 75-MHz@3.3-V clock. The 64-point and 8,192-point FFT's can be computed in $2.25-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of various OFDM-based systems.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.393-396
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• 2009

This paper describes a design of variable-length FFT/IFFT processor for OFDM-based communication systems. The designed FFT/IFFT processor adopts the in-place single-memory architecture, and uses a hybrid structure of radix-4 and radix-2 DIF algorithms to accommodate FFT lengths of $N=64{\times}2^k$ ($0{\leq}k{\leq}7$). To achieve both memory size reduction and the improved SQNR, a two-step conditional scaling technique is devised, which conditionally scales the intermediate results of each computational stage. The performance analysis results show that the average SQNR's of 64~8,192-point FFT's are over 60-dB. The processor synthesized with a $0.35-{\mu}m$ CMOS cell library can operate with 75-MHz@3.3-V clock, and 64-point and 8,192-point FFT's can be computed in $2.55-{\mu}s$ and $762.7-{\mu}s$, respectively, thus it satisfies the specifications of wireless LAN, DMB, and DVB systems.

• Journal of Information Technology Services
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• v.12 no.4
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• pp.369-380
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• 2013

The advent of the state-of-the-art technologies such as cloud computing and big data processing stimulates the provision of various new IT services, which implies that more servers are required to support them. However, the need for more servers will lead to more energy consumption and the efficient use of energy in the computing environment will become more important. The next generation nonvolatile RAM has many desirable features such as byte addressability, low access latency, high density and low energy consumption. There are many approaches to adopt them especially in the area of the file system involving storage devices, but their focus lies on the improvement of system performance, not on energy reduction. This paper suggests a novel approach for energy reduction in which the MRAM-based SSD is utilized as a storage device instead of the hard disk and a downsized page is adopted instead of the 4KB page that is the size of a page in the ordinary file system. The simulation results show that energy efficiency of a new approach is very effective in case of accessing the small number of bytes and is improved up to 128 times better than that of NAND Flash memory.

• Structural Engineering and Mechanics
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• v.38 no.4
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• pp.429-441
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• 2011

In large-scale problem, a huge size of computational resources is needed for a reliable solution which represents the detailed description of dynamic behavior. Recently, eigenvalue reduction schemes have been considered as important technique to resolve computational resource problems. In addition, the efforts to advance an efficiency of reduction scheme leads to the development of the multi-level system condensation (MLSC) which is initially based on the two-level condensation scheme (TLCS). This scheme was proposed for approximating the lower eigenmodes which represent the global behavior of the structures through the element-level energy estimation. The MLSC combines the multi-level sub-structuring scheme with the previous TLCS for enhancement of efficiency which is related to computer memory and computing time. The present study focuses on the implementation of the MLSC on the direct time response analysis and the frequency response analysis of structural dynamic problems. For the transient time response analysis, the MLSC is combined with the Newmark's time integration scheme. Numerical examples demonstrate the efficiency of the proposed method.

• ETRI Journal
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• v.31 no.4
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• pp.393-398
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• 2009

The operation of a first-order 2-bit adaptive sigma-delta modulation system is described and discussed in this paper. The system operation is based on the combination of both "memory" and "look-ahead" estimation in the employed step-size adaptation algorithm of the basic quantizer. In comparison to simple systems and other adaptive sigma-delta systems, computer simulation results show that these features of the described system are responsible for the high SNR values and the extended dynamic range achieved for AC signals as well as the noise power reduction of almost 10 dB and the complete elimination of the idle tones for DC signals. However, such an advantageous performance requires the least possible multiplicative error accumulation, and this cannot be achieved without analog circuits of the highest possible accuracy.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2011.04a
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• pp.339-344
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• 2011

In the past much effort has been made to utilize advanced computational fluid dynamic (CFD) programs for aeroelastic simulations and analysis. However, it is limited in the field of unsteady aeroelasticity due to enormous size of computer memory and unreasonably long CPU time. Recently, AAEMS(Aerodynamics is Aeroelasticity minus Structure) was developed for linear time-invariant, coupled fluid-structure systems. In this paper, to demonstrate further the efficiency and accuracy of the new model reduction method, we successfully examine AGARD 445.6 wing modeled by FLUENT CFD, FSIPRO3D and NASTRAN FEM(Finite Element Method) programs. Using the ROM(Reduced Order Modeling) one can predict flutter boundary as a function of the dynamic pressure.