• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.117-123
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• 2016

In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.3
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• pp.93-98
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• 2022

Recently, fast storage media such as Optane have emerged, and memory system configurations designed for disk storage should be reconsidered. In this paper, we analyze the effect of the page size on the memory system performances when fast storage is adopted. Based on this, we design a page size model that can guide an appropriate page size for given workloads in virtualized environments. Configuring different page sizes for various workloads is not an easy matter in traditional systems, but due to the widespread adoption of cloud systems, page sizing performed in our model is feasible for virtual machines, which are generated for executing specific workloads. Simulation experiments under various virtual machine scenarios show that the proposed model improves the memory access time significantly by configuring page sizes for given workloads.

• The Journal of Korean Association of Computer Education
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• v.15 no.3
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• pp.37-47
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• 2012

One of the major goals in high school Informatics is for students to develop creative problem-solving abilities based on knowledge on computer science. Thus, the contents of the textbooks should be accurate and appropriate. However, we discovered that the current Informatics textbooks contain the untrue and/or inappropriate descriptions of main memory and virtual memory. The textbooks describe that main memory is composed of RAM and ROM. The virtual memory is described as a technique in which a part of the secondary storage is utilized as main memory to execute an application of which size is larger than that of main memory. In this study, we attempted to uncover the root causes of the fallacies, and suggest the accurate explanations by comparing with renowned books adopted in most schools worldwide including USA. Our study reveals that it is inappropriate to include ROM in main memory from the memory hierarchy perspective. Virtual memory is a technique that provides convenience to programmers, through which an operating system loads the necessary portion of a program from secondary storage to main memory. As for the advantages of virtual memory in the current computer systems, the focus should be on providing the effective multitasking capability, rather than on executing a larger program than the size of main memory. We suggest that it is appropriate to exclude virtual memory in textbooks considering its complexity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.224-240
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• 1996

It is common sense for at least one or more levels of cache memory to be used in these day's computer systems. In this paper, the impact of the internal cache memory organization on the performance of the computer is investigated by using a simulator program, which is wirtten by authors and run on SUN SPARC workstation, with several real execution, with several real execution trace files. 280 cache organizations have been simulated using n-way set associative mapping and LRU(Least Recently Used) replacement algorithm with write allocation policy. As a result, 16-way setassociative cache is the best configuration, and when we select 256KB cache memory and 64 byte line size, the bus traffic ratio was decreased compared to that of the noncache system so that a single bus could support almost 7 processors without any delay and degradationof high ratio(hit ratio was 99.21%). The smaller the line size we choose, the little lower hit ratio we can get, but the more processors can be supported by a single bus(maximum 18 processors). Therefore, using a proper cache memory organization can make a single bus structure be able to support multiple processors without any performance degradation.

• Journal of the Korea Computer Industry Society
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• v.2 no.2
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• pp.211-218
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• 2001

In this paper, we propose the structure of utilizing the memory map, which is using not conventional DRAM but SDRAM, for the hardware implementation of frame memory interface module to the video encoder. As reducing the size of memory map and interface buffer within the same bus, the hardware complexity is improved and the hardware size is minimized as simplifying the interface logic. The conventional system is wasted access time, because of accessing randomly stored data in order to store and output the memories in macro-block unit. therefore the method, which is proposed in this paper, can be effectively reducing the access time of memory, because of the data is stored and processed by line unit.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.1
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• pp.88-97
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• 2000

We have proposed and analysed a novel Lookup Algorithm which had a short switching speed and tiny memory size for IP router. This algorithm could simply be implemeted by a hardware with SRAM because of simple structure. This Lookup scheme needs 1${\sim}$3 memory access times. When we simulated with 40,000 routing record obtained from IPMA Website, the maximum memory size of this algorithm was 316KB(the offset threshold for compression algorithm was 8). When we simulated by HDL using ALTERA EPM7256 series and 100MHz clock and SRAM of 10ns access time, the total lookup time was 45ns for two memory access, 175ns for three memory access.

• Proceedings of the Korean Society of Tribologists and Lubrication Engineers Conference
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• 2004.11a
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• pp.330-330
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• 2004

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.19-22
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• 2003

Class area is a portion of memory where the constants, fields, and codes of the classes loaded into the Java virtual machine are kept. Knowing the site of the class area is very important especially for embedded Java system with limited memory resources. This paper induces a formula which makes it possible estimate the size of the area. The formula needs some constant values specific to target JVM implementation. We also show that these values can be found using some simple probe classes. An experimental result is included in this paper to confirm the correctness of our approach.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.825-828
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• 2005

In this paper, we propose a new nonvolatile unit memory cell and proposal peripheral circuit using the polymer material. Memory that relies on bistable behavior- having tow states associated with different resistances at the same applied voltage - has attracted much interest because of its nonvolatile properties. Such memory may also have other merits, including simplicity of structure and manufacturing, and the small size of memory cells. We have plotted the load line graphs for the use of a polymer memory character, hence we have designed in the band-gap reference shape of a write/erase drive, and then designed in the 2-stage differential amplifier shape of a sense amplifier in the consideration of a low current characteristic of a polymer memory cell. The simulation result shows that is has high gain about 80dB by sensing the very small current.