• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.3
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• pp.699-707
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• 2016

This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a $0.18{\mu}m$ digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.9
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• pp.407-415
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• 2007

In parallel cluster computing systems, the efficiency of communication between computing nodes is one of important factors that decide overall system performance. Accordingly, many researchers have studied on high-performance inter-node communication. The recently launched multi-core processor, however. increases the importance of intra-node communication as well because the more the number of cores in a node, the more the number of parallel processes running in the same node. Though there have been studies on intra-node communications, these have limited considerations on the state-of-the-art systems. In this paper, we propose a Linux kernel module that minimizes the number of data copy by exploiting the memory mapping mechanism for high-performance intra-node communication. The proposed kernel module supports the Linux kernel version 2.6. The performance measurements over a multi-core system present that the proposed kernel module can achieve lower latency up to 62% and higher throughput up to 144% than an existing kernel module approach. In addition, the measurements reveal that the performance of intra-node communication can vary significantly based on whether the cores that run the communication processes are belong to the same processor package (i.e., sharing the L2 cache).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.6
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• pp.333-340
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• 2014

Despite the security weakness of reusing passwords, many Internet users are likely to use a single ID and password on various sites to avoid the inconvenience of remembering multiple credentials. This paper proposes a scheme for securely storing, retrieving, and updating randomly chosen (ID, password) pairs by using smart cards as secure and portable storages. The scheme makes a user free from remembering her (ID, password) pairs for Internet accesses. By splitting and scattering the (ID, password) pairs of a user across the user's smart card memory and a remote server's storage, it can protect the logon credentials even from the theft or loss of the smart card. Also, a user, if deemed necessary, can issue and let the server to delete all information belonging to the user. Hence even an attacker who cracked the smart card memory would not be able to obtain any (ID, password) pair of the victim thereafter. The scheme requires a user to input a site information and pass-phrase to her smart card to obtain the logon credentials, but it should be an acceptable overhead considering the benefits of not remembering the freely chosen (ID, password) pairs at all.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.128-133
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• 2008

Phase-change random access memory (PRAM) chip cell phase of amorphous state is rapidly changed to crystal state above 160 Celsius degree within several seconds during Infrared (IR) reflow. Thus, on-board programming method is considered for PRAM chip programming. We demonstrated the functional 512Mb PRAM with 90nm technology using several novel core circuits, such as metal-2 line based global row decoding scheme, PN-diode cells based BL discharge (BLDIS) scheme, and PMOS switch based column decoding scheme. The reverse-state standby current of each PRAM cell is near 10 pA range. The total leak current of 512Mb PRAM chip in standby mode on discharging state can be more than 5 mA. Thus in the proposed BLDIS control, all bitlines (BLs) are in floating state in standby mode, then in active mode, the activated BLs are discharged to low level in the early timing of the active period by the short pulse BLDIS control timing operation. In the conventional sense amplifier, the simultaneous switching activation timing operation invokes the large coupling noise between the VSAREF node and the inner amplification nodes of the sense amplifiers. The coupling noise at VSAREF degrades the sensing voltage margin of the conventional sense amplifier. The merit of the proposed sense amplifier is almost removing the coupling noise at VSAREF from sharing with other sense amplifiers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.1
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• pp.37-44
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• 2009

This paper describes a new tiled display framework called, iTDF (Interactive Tiled Display Framework), that is designed to support rapid construction of the interactive digital 3D contents running on top of the cluster-based tiled display. This framework allows synchronizing the rendering slaves, sharing software's state over the network, the features, such as, launching multiple applications on a cluster-based computers, moving and resizing windows, synchronization of rendering slaves, distributed shared memory, and unified input interface. This paper analyzes the requirements of the framework and describes the design and implementation of the framework. A couple desktop-based applications are ported with the new iTDF and to find out the usefulness and usability of the framework.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.9
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• pp.86-94
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• 1998

This paper proposes a new fast block-matching algorithm, named MFSS(Modified Four-Step Search) algorithm, which has better performance and is more adequate for hardware realization than the existing fast algorithms. The proposed algorithm is suitable for hardware realization since it has a unique regularity during the search procedure. It is shown from simulation results that its performance is close to that of FS(Full Search) algorithm. This paper also proposes a VLSI architecture and presents some design results of a motion estimator and compensator which adopted the MFSS algorithm. The important aspects considered in designing a motion estimator and compensator are hardware complexity of design results, and total delay needed to generate the motion compensated data after finding the motion vectors. Hardware complexity is minimized by using just nine PE(Process Element)'s, and total delay is minimized by sharing search memory of the motion estimator and compensator.

• Journal of IKEEE
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• v.22 no.3
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• pp.522-531
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• 2018

A public-key cryptography processor EC-RSA was designed, which integrates a 224-bit prime field elliptic curve cryptography (ECC) defined in the FIPS 186-2 as well as RSA with 2048-bit key length into a single hardware structure. A finite field arithmetic core used in both scalar multiplication for ECC and exponentiation for RSA was designed with 32-bit data-path. A lightweight implementation was achieved by an efficient hardware sharing of the finite field arithmetic core and internal memory for ECC and RSA operations. The EC-RSA processor was verified by FPGA implementation. It occupied 11,779 gate equivalents (GEs) and 14 kbit RAM synthesized with a 180-nm CMOS cell library and the estimated maximum clock frequency was 133 MHz. It takes 867,746 clock cycles for ECC scalar multiplication resulting in the estimated throughput of 34.3 kbps, and takes 26,149,013 clock cycles for RSA decryption resulting in the estimated throughput of 10.4 kbps.

• Journal of Intelligence and Information Systems
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• v.14 no.4
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• pp.1-18
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• 2008

By using previous similar case plans, the case-based planning (CBP) systems can generate efficiently plans for new problems. However, most existing CBP systems show limited functionalities for case retrieval and case generalization. Moreover, they do not allow their users to participate in the process of plan generation. To support efficient memory use and case retrieval, the proposed case-based planning system, JCBP, groups the set of cases sharing the same goal in each domain into individual case bases and maintains indexes to these individual case bases. The system applies the heuristic knowledge automatically extracted from the problem model to the case adaptation phase. It provides a sort of case generalization through goal regression. Also JCBP can operate in an interactive mode to support a mixed-initiative planning. Since it considers and utilizes user's preference and knowledge for solving the given planning problems, it can generate solution plans satisfying more user's needs and reduce the complexity of plan generation.

• Journal of KIISE:Software and Applications
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• v.34 no.5
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• pp.465-475
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• 2007

With the spread of Internet, web users express their daily life by articles, pictures and cartons to recollect personal memory or to share their experience. For the easier recollection and sharing process, this paper proposes diverse cartoon generation methods using the landmark lists which represent the behavior and emotional status of the user. From the priority and causality of each landmark, critical landmark is selected for composing the cartoon scenario, which is revised by story ontology. Using similarity between cartoon images and each landmark in the revised scenario, suitable cartoon cut for each landmark is composed. To make cartoon story more diverse, weather, nightscape, supporting character, exaggeration and animation effects are additionally applied. Through example scenarios and usability tests, the diversity of the generated cartoon is verified.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.61-68
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• 2008

In this paper, we propose the VLSI design of Multi-Format Video Decoder (MFD) to support video codec standards such as MPEG-2, MPEG-4, H.264 and VC-1. The target of the proposed MFD is the Full HD (High Definition) video processing needed for the high-end D-TV SoC (System-on-Chip). The size of the design is reduced by sharing the common large-size resources such as the RISC processor and the on-chip memory among the different codecs. In addition, a detachable architecture is introduced in order to easily add or remove the codecs. The detachable architecture preserves the stability of the previously designed and verified codecs. The size of the design is about 2.4 M gates and the operating clock frequency is 225MHz in the Samsung 65nm process. The proposed MFD supports more than Full-HD (1080p@30fps) video decoding, and the largest number of video codec standards known so far.