• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.59-65
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• 2016

Performance optimization of applications with massive stream data processing has been performed by considering I/O data coherency problem where a memory is shared between processors and hardware accelerators. A formula for performance analyses is derived based on profiling results of system-level simulations. Our experimental results show that overall performance was improved by 1.40 times on average for various image sizes. Also, further optimization has been performed based on the parameters appeared in the derived formula. The final performance gain was 3.88 times comparing to the original design and we can find that the performance of the design with cacheable shared memory is not always.

• The KIPS Transactions:PartA
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• v.9A no.2
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• pp.147-162
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• 2002

Multi-processor system with fast I/O devices improves processing performance and reduces the bottleneck by I/O concentration. In the system, the Performance influenced by shared memory used for exchanging data between processors varies with configuration and utilization. This paper suggests a prediction model for buffer and shared memory optimization under interrupt recognition method using mailbox. Ethernet (IEEE 802.3) packets are used as the input of system and the amount of utilized memory is measured for different network bandwidth and burstiness. Some empirical studies show that the amount of buffer and shared memory varies with packet concentration rate as well as I/O bandwidth. And the studies also show the correlation between two memories.

• Smart Structures and Systems
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• v.19 no.4
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• pp.341-350
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• 2017

Based on the super elastic properties of the shape memory alloy (SMA) and the inverse piezoelectric effect of piezoelectric (PZT) ceramics, a kind of hybrid semi-active control device was designed and made, its mechanical properties test was done under different frequency and different voltage. The local search ability of genetic algorithm is poor, which would fall into the defect of prematurity easily. A kind of adaptive immune memory cloning algorithm(AIMCA) was proposed based on the simulation of clone selection and immune memory process. It can adjust the mutation probability and clone scale adaptively through the way of introducing memory cell and antibody incentive degrees. And performance indicator based on the modal controllable degree was taken as antigen-antibody affinity function, the optimization analysis of damper layout in a space truss structure was done. The structural seismic response was analyzed by applying the neural network prediction model and T-S fuzzy logic. Results show that SMA and PZT friction composite damper has a good energy dissipation capacity and stable performance, the bigger voltage, the better energy dissipation ability. Compared with genetic algorithm, the adaptive immune memory clone algorithm overcomes the problem of prematurity effectively. Besides, it has stronger global searching ability, better population diversity and faster convergence speed, makes the damper has a better arrangement position in structural dampers optimization leading to the better damping effect.

• Journal of Information Processing Systems
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• v.14 no.5
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• pp.1237-1253
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• 2018

Harmony search algorithm is an emerging meta-heuristic optimization algorithm, which is inspired by the music improvisation process and can solve different optimization problems. In order to further improve the performance of the algorithm, this paper proposes an improved harmony search algorithm. Key parameters including harmonic memory consideration (HMCR), pitch adjustment rate (PAR), and bandwidth (BW) are optimized as the number of iterations increases. Meanwhile, referring to the genetic algorithm, an improved method to generate a new crossover solutions rather than the traditional mechanism of improvisation. Four complex function optimization and pressure vessel optimization problems were simulated using the optimization algorithm of standard harmony search algorithm, improved harmony search algorithm and exploratory harmony search algorithm. The simulation results show that the algorithm improves the ability to find global search and evolutionary speed. Optimization effect simulation results are satisfactory.

• Structural Engineering and Mechanics
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• v.77 no.6
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• pp.779-795
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• 2021

In the recent decades, various optimization algorithms have been considered for the optimization of structures. In this research, a new enhanced algorithm is used for the size and topology optimization of truss structures. This algorithm, which is obtained from the combination of Crow Search Algorithm (CSA) and the Cellular Automata (CA) method, is called CA-CSA method. In the first iteration of the CA-CSA method, some of the best designs of the crow's memory are first selected and then located in the cells of CA. Then, a random cell is selected from CA, and the best design is chosen from the selected cell and its neighborhood; it is considered as a "local superior design" (LSD). In the optimization process, the LSD design is used to modify the CSA method. Numerical examples show that the CA-CSA method is more effective than CSA in the size and topology optimization of the truss structures.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.801-804
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• 2009

In this paper, the Linux kernel memory map was analyzed as the approach to Improving performance for Embedded Linux system. Since the Linux kernel memory map supporting a stability and various H/W platforms and in which it becomes to the general purpose system with optimization manages the role of being important in the booting time and the efficient system utilization of resources, the analysis of the kernel memory map is required for the performance improvement of the Embedded Linux system in which it is restrictive the resources. According to the analysis result, and of the Linux kernel memory, the booting speed of and improvement of the memory efficiency were confirmed. It is therefore considered that the proposed in this paper and kernel memory allocation method are suitable to the memory availability improvement of the Embedded Linux system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.40-41
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• 2005

In this study, we proposed CMP micro-scratches generated by contaminative particle which existed on the wafer surface prior to CMP process. The CMP micro-scratches are one of the slurry abrasive related damage. To reduce the micro-scratches, research efforts have been devoted to the optimization of slurry abrasive size distribution. In addition of slurry abrasive, it was found that contaminative particles also were major CMP micro-scratch source.

• Structural Engineering and Mechanics
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• v.55 no.5
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• pp.901-911
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• 2015

The goal of this study is to investigate computational convergence of optimal solutions, with respect to optimality criteria (OC) method and methods of moving asymptotes (MMA) as optimization model for non-linear programming of material topology optimization using an acceleration method that makes design variables rapidly move toward almost 0 and 1 values. 99 line topology optimization MATLAB code uses loop vectorization and memory pre-allocation as properly exploiting the strengths of MATLAB and moves portions of code out of the optimization loop so that they are only executed once as restructuring the program. Numerical examples of a simple beam under a lateral load and a given material density limitation provide merits and demerits of the present OC and MMA for 99 line topology optimization code of continuous material topology optimization design.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.7
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• pp.508-519
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• 2007

Flash memory based storage has been used in various mobile systems and now is to be used in Laptop computers in the name of Solid State Disk. The Flash memory has not only merits in terms of weight, shock resistance, and power consumption but also limitations like erase-before-write property. To overcome these limitations, Flash memory based storage requires special address mapping software called FTL(Flash-memory Translation Layer), which often performs merge operation for block recycling. In order to reduce block recycling cost in NAND Flash memory based storage, we introduce another block recycling scheme which we call migration. As a result, the FTL can select either merge or migration depending on their costs for each block recycling. Experimental results with Postmark benchmark and embedded system workload show that this cost-based selection of migration/merge operation improves the performance of Flash memory based storage. Also, we present a solution of macroscopic optimal migration/merge sequence that minimizes a block recycling cost for each migration/merge combination period. Experimental results show that the performance of Flash memory based storage can be more improved by the macroscopic optimization than the simple cost-based selection.

• The KIPS Transactions:PartA
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• v.18A no.3
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• pp.109-114
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• 2011

We describe a technique for automatically proving compiler optimizations sound, meaning that their transformations are always semantics-preserving. As is well known, IR (Intermediate Representation) optimization is an important step in a compiler backend. But unfortunately, it is difficult to detect and debug the IR optimization errors for compiler developers. So, we introduce a C level error check system for detecting the correctness of these IR transformation techniques. In our system, we first create an IR-to-C converter to translate IR to C code before and after each compiler optimization phase, respectively, since our technique is based on the Memory Comparison-based Clone(MeCC) detector which is a tool of detecting semantic equivalency in C level. MeCC accepts only C codes as its input and it uses a path-sensitive semantic-based static analyzer to estimate the memory states at exit point of each procedure, and compares memory states to determine whether the procedures are equal or not. But MeCC cannot guarantee two semantic-equivalency codes always have 100% similarity or two codes with different semantics does not get the result of 100% similarity. To increase the reliability of the results, we describe a technique which comprises how to generate C codes in IR-to-C transformation phase and how to send the optimization information to MeCC to avoid the occurrence of these unexpected problems. Our methodology is illustrated by three familiar optimizations, dead code elimination, instruction scheduling and common sub-expression elimination and our experimental results show that the C level error check system is highly reliable.