• IEMEK Journal of Embedded Systems and Applications
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• v.18 no.1
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• pp.31-40
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• 2023

Recent advances in flash technologies, such as 3D processing and multileveling schemes, have successfully increased the flash capacity. Unfortunately, these technology advances significantly degrade flash's reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose an asymmetric BER-aware reliability optimization technique (aBARO), new flash optimization that improves the flash reliability. To this end, we first reveal that bit errors of 3D NAND flash memory are highly skewed among flash cell states. The proposed aBARO exploits the unique per-state error model in flash cell states by selecting the most error-prone flash states and by forming narrow threshold voltage distributions (for the selected states only). Furthermore, aBARO is applied only when the program time (tPROG) gets shorter when a flash cell becomes aging, thereby keeping the program latency of storage systems unchanged. Our experimental results with real 3D MLC and TLC flash devices show that aBARO can effectively improve flash reliability by mitigating a significant number of bit errors. In addition, aBARO can also reduce the read latency by 40%, on average, by suppressing the read retries.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.7 no.1
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• pp.7-14
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• 2003

The main concern of this paper is to develop a new class of quasi-newton methods. These methods are intended for use whenever memory space is a major concern and, hence, they are usually referred to as limited memory methods. The methods developed in this work are sensitive to the choice of the memory parameter ${\eta}$ that defines the amount of past information stored within the Hessian (or its inverse) approximation, at each iteration. The results of the numerical experiments made, compared to different choices of these parameters, indicate that these methods improve the performance of limited memory quasi-Newton methods.

• Journal of applied mathematics & informatics
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• v.24 no.1_2
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• pp.367-376
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• 2007

In this paper we consider the global convergence of a new super memory gradient method for unconstrained optimization problems. New trust region radius is proposed to make the new method converge stably and averagely, and it will be suitable to solve large scale minimization problems. Some global convergence results are obtained under some mild conditions. Numerical results show that this new method is effective and stable in practical computation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.5 no.1
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• pp.60-69
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• 1980

The computerized analysis of complicated circuits requires large memory capacity and considerable length of time. In order to enhance the efficiency of memory capacity and the executing time, Sparse Matrix is applied to the solution of simultaneous equations required for the analysis of amplification circuit. The optimization Subroutine, FMFP is utilized for the decision of optimum element parameters of an equalizer amplifier.

• Journal of Korea Game Society
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• v.11 no.1
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• pp.147-157
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• 2011

Webcam doesn't perform memory-alignment in order to reduce the transmission time of image data. Memory-unaligned image data is unsuitable for the processing on GPU. Accordingly, we convert it to available color format for optimization in high speed image processing. In this paper, we propose a technique that accelerates webcam's color format conversion by using NVDIA CUDA. We propose an optimization which is about memory accesses and thread composition, also evaluate memory and computing performance for verifying a hypothesis which is the performance of the proposed architecture and optimizing degree on low-performance GPU. Following the optimization technique, we show performance improvements over maximum 68 percent.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.3
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• pp.630-637
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• 2018

Harmony search (HS) is a recently developed metaheuristic optimization algorithm. HS is inspired by the process of musical improvisation and repeatedly searches for the optimal solution using three operations: random selection, memory recall (or harmony memory consideration), and pitch adjustment. HS has been applied by many researchers in various fields. The increasing complexity of real-world optimization problems has created enormous challenges for the current technique, and improved techniques of optimization algorithms and HS are required. We propose an improved clustering harmony search (ICHS) that uses a clustering technique to group solutions in harmony memory based on their objective function values. The proposed ICHS performs modified harmony memory consideration in which decision variables of solutions in a high-ranked cluster have higher probability of being selected than those in a low-ranked cluster. The ICHS is demonstrated in various optimization problems, including mathematical benchmark functions and water distribution system pipe design problems. The results show that the proposed ICHS outperforms other improved versions of HS.

• International Journal of Internet, Broadcasting and Communication
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• v.9 no.1
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• pp.29-34
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• 2017

Over the past several decades, embedded system and flight control computer technologies have been evolved to meet the diverse needs of the mobile device market. Current embedded systems are at the heart of technologies that can take advantage of small-sized specialized hardware while still providing high-efficiency performance at low cost. One of these key technologies is multiple memory banks. For example, a dual memory bank can provide two times more memory bandwidth in the same memory space. This benefit take lower cost to provide the same bandwidth. However, there is still few software technologies to support the efficient use of multiple memory banks. In this study, we present a technique to efficiently exploit multiple memory banks by software support. Specifically, our technique use an interference graph to optimally allocate data to different memory banks by an optimizing compiler. As a result, the execution time can be improved upto 7% with the proposed technique.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 1998.04a
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• pp.273-279
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• 1998

An immune system has powerful abilities such as memory, recognition and learning to respond to invading antigens, and is applied to many engineering algorithm recently. In this paper, the combined optimization algorithm is proposed for multi-optimization problem by introducing the capability of the immune system that controls the proliferation of clones to the genetic algorithm. The optimizing ability of the proposed optimization algorithm is identified by using two multi-peak functions which have many local optimums and optimization of the unbalance response function for rotor model.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.4
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• pp.353-360
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• 2002

Methods for automatic tuning of PID controllers have been on of the results of the active research on control. The proposed controller also is auto-tuning of PID controller The proposed immune algorithm has an uncomplicated structure and memory-cell mechanism as the optimization algorithm which imitates the principle of humoral immune response. We use the proposed algorithm to solve optimization of PID controller parameters. Up to now, the applications of immune algorithm have been optimization problems with non-varying system parameters. Therefore the usefulness of memory-cell mechanism in immune algorithm is without. And research of memory-cell mechanism does not give us entire satisfaction. This paper proposes the immune algorithm using a memory-cell mechanism which can be the application of system with nonlinear varying parameters. To verify performance of the proposed immune algorithm, the speed control of nonlinear DC motor are performed. The results of Computer simulations represent that the proposed immune algorithm shows a fast convergence speed and a good control performances under the varying system parameters.

• Journal of KIISE
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• v.44 no.11
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• pp.1130-1137
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• 2017

The multi-leveling technique that stores multiple bits in a single memory cell has significantly improved the density of NAND flash memory along with shrinking processes. However, because of the side effects of the multi-leveling technique, the average write performance of MLC NAND flash memory is degraded more than twice that of SLC NAND flash memory. In this paper, we introduce existing cross-layer optimization techniques proposed to improve the performance of MLC NAND flash-based storages, and propose a new integration technique that overcomes the limitations of existing techniques by exploiting their complementarity. By fully exploiting the performance asymmetry in MLC NAND flash devices at the flash translation layer, the proposed technique can handle many write requests with the performance of SLC NAND flash devices, thus significantly improving the performance of NAND flash-based storages. Experimental results show that the proposed technique improves performance 39% on average over individual techniques.