• International Commerce and Information Review
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• v.9 no.2
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• pp.423-439
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• 2007

The purpose of this study was to analyze market competitiveness of Korean and Chinese computer parts industry in the between two countries' market by using Index of Export Bias and Market Comparative Advantage Index. For attaining the purpose of study, we classified the computer parts which exported to the two countries' market and the imported products as the memory devices and input/output peripheral devices. Analyzing period was 2001-2006. The analysis of Korean results of Index of Export Bias indicated that memory devices represented low overall numerical value and the Chinese results of Index of Export Bias indicated that memory devices represented high gradual numerical value. On the other hand, Korean input/output peripheral devices have been increasing steadily for analysis period and China input/output peripheral devices have been decreasing steadily for analysis period. Additional results indicated that the Korean and China computer parts which gained market competitiveness between two countries market were as follows. Korean memory devices have been losing competitiveness in the China market steadily and Chinese memory devices have been acquire competitiveness in the Korean market gradually. In input/output peripheral devices case, Korean products represented powerful competitiveness in the China market and Chinese products have been gaining competitiveness in the Korea market.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.391-406
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• 2014

The performance of General-Purpose computation on Graphics Processing Units (GPGPU) is heavily dependent on the memory access behavior. This sensitivity is due to a combination of the underlying Massively Parallel Processing (MPP) execution model present on GPUs and the lack of architectural support to handle irregular memory access patterns. Application performance can be significantly improved by applying memory-access-pattern-aware optimizations that can exploit knowledge of the characteristics of each access pattern. In this paper, we present an algorithmic methodology to semi-automatically find the best mapping of memory accesses present in serial loop nest to underlying data-parallel architectures based on a comprehensive static memory access pattern analysis. To that end we present a simple, yet powerful, mathematical model that captures all memory access pattern information present in serial data-parallel loop nests. We then show how this model is used in practice to select the most appropriate memory space for data and to search for an appropriate thread mapping and work group size from a large design space. To evaluate the effectiveness of our methodology, we report on execution speedup using selected benchmark kernels that cover a wide range of memory access patterns commonly found in GPGPU workloads. Our experimental results are reported using the industry standard heterogeneous programming language, OpenCL, targeting the NVIDIA GT200 architecture.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.256-261
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• 2003

A memory industry is developing rapidly according to the period of the ubiquitous to approach. According to the development of a memory industry, the efficiency of the manufacture is becoming the serious consideration. DC parameter test system was a development low in this research for an efficiency increase of the manufacture. DC parameter test system increase of the manufacture. In the method to measure the output after permit volt and current at element.

• Electronics and Telecommunications Trends
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• v.38 no.5
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• pp.23-33
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• 2023

With the widespread demand from data-intensive tasks such as machine learning and large-scale databases, the amount of data processed in modern computing systems is increasing exponentially. Such data-intensive tasks require large amounts of memory to rapidly process and analyze massive data. However, existing computing system architectures face challenges when building large-scale memory owing to various structural issues such as CPU specifications. Moreover, large-scale memory may cause problems including memory overprovisioning. The Compute Express Link (CXL) allows computing nodes to use large amounts of memory while mitigating related problems. Hence, CXL is attracting great attention in industry and academia. We describe the overarching concepts underlying CXL and explore recent research trends in this technology.

• Journal of the Korea Society of Computer and Information
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• v.20 no.11
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• pp.1-8
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• 2015

Flash memory has advantages in that it is fast access speed, low-power, and low-price. Therefore, they are widely used in electronics industry sectors. However, the flash memory has weak points, which are the limited number of erase operations and non-in-place update problem. To overcome the limited number of erase operations, many wear leveling techniques are studied. They use many tables storing information such as erase count of blocks, hot and cold block indicators, reference count of pages, and so on. These tables occupy some space of main memory for the wear leveling techniques. Accordingly, they are not appropriate for low-power devices limited main memory. In order to resolve it, a wear leveling technique using bit array and Bit Set Threshold (BST) for flash memory. The proposing technique reduces the used space of main memory using a bit array table, which saves the history of block erase operations. To enhance accuracy of cold block information, we use BST, which is calculated by using the number of invalid pages of the blocks in a one-to-many mode, where one bit is related to many blocks. The performance results illustrate that the proposed wear leveling technique improve life time of flash memory to about 6%, compared with previous wear leveling techniques using a bit array table in our experiment.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.122-130
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• 2013

The demand and the supply are increasing sharply in accordance with the growth of the Memory Semiconductor Industry. The Flash Memory above all is being utilized substantially in the Industry of smart phone, the tablet PC and the System on Chip (SoC). The Flash Memory is divided into the NOR-type Flash Memory and the NAND-type Flash Memory. A lot of study such as the Built-In Self Test (BIST), the Built-In Self Repair (BISR) and the Built-In Redundancy Analysis (BIRA), etc. has been progressed in the NOR-type fash Memory, the study for the Built-In Self Test of the NAND-type Flash Memory has not been progressed. At present, the pattern test of the NAND-type Flash Memory is being carried out using the outside test equipment of high price. The NAND-type Flash Memory is being depended on the outside equipment as there is no Built-In Self Test since the erasure of block unit, the reading and writing of page unit are possible in the NAND-type Flash Memory. The Built-In Self Test equipped with 2 kinds of finite state machine based structure is proposed, so as to carry out the pattern test without the outside pattern test equipment from the NAND-type Flash Memory which carried out the test dependant on the outside pattern test equipment of high price.

• Laboraroty Animal Research
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• v.34 no.4
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• pp.317-328
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• 2018

Cognitive impairment responses are important research topics in the study of degenerative brain diseases as well as in understanding of human mental activities. To compare response to scopolamine (SPL)-induced cognitive impairment, we measured altered parameters for learning and memory ability, inflammatory response, oxidative stress, cholinergic dysfunction and neuronal cell damages, in Korl:ICR stock and two commercial breeder stocks (A:ICR and B:ICR) after relevant SPL exposure. In the water maze test, Korl:ICR showed no significant difference in SPL-induced learning and memory impairment compared to the two different ICRs, although escape latency was increased after SPL exposure. Although behavioral assessment using the manual avoidance test revealed reduced latency in all ICR mice after SPL treatment as compared to Vehicle, no differences were observed between the three ICR stocks. To determine cholinergic dysfunction induction by SPL exposure, activity of acetylcholinesterase (AChE) assessed in the three ICR stocks revealed no difference of acetylcholinesterase activity. Furthermore, low levels of superoxide dismutase (SOD) activity and high levels of inflammatory cytokines in SPL-treated group were maintained in all three ICR stocks, although some variations were observed between the SPL-treated groups. Neuronal cell damages induced by SPL showed similar response in all three ICR stocks, as assessed by terminal deoxynucleotidyl transferase dUTP nick end labeling (TUNEL) assay, Nissl staining analysis and expression analyses of apoptosis-related proteins. Thus, the results of this study provide strong evidence that Korl:ICR is similar to the other two ICR. Stocks in response to learning and memory capacity.

• Journal of Integrative Natural Science
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• v.14 no.4
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• pp.189-196
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• 2021

Recently, as a countermeasure for cyber breach attacks and confidential leak incidents on PC hard disk memory storage data of the metaverse industry, it is required when reviewing and developing a remote-based regular/real-time monitoring and analysis security system. The reason for this is that more than 90% of information security leaks occur on edge-end PCs, and tangible and intangible damage, such as an average of 1.20 billion won per metaverse industrial security secret leak (the most important facts and numerical statistics related to 2018 security, 10.2018. the same time as responding to the root of the occurrence of IT WORLD on the 16th, as it becomes the target of malicious code attacks that occur in areas such as the network system web due to interworking integration when building IT infrastructure, Deep-Access-based regular/real-time remote. The concept of memory analysis and audit system is key.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.111-129
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• 2005

Pop provides OEMs and EMS with a platform to cost effectively expand options for logic + memory 3D integration - Expands device options by simplifying business logistics of stacking - Integration controlled at the system level to best match stacked combinations with system requirements - Eliminates margin stacking and expands technology reuse - Helps manage the huge cost impacts associated with increasing demand for multi media processing and memory. PoP is well timed to enable and leverage: - Mass customization of systems for different use (form, fit and function) requirements o Bband and apps processor + memory stack platforms - Logic transition to flip chip enables PoP size reduction o Area and height reduction. Industry standardization is progressing. Amkor provides full turn-key support for base package, memory package and full system integration.

• Journal of the Korea Computer Industry Society
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• v.6 no.2
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• pp.295-304
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• 2005

This paper presents the problem of exhaustive test generation for detection of coupling faults between cells in word-oriented memories. According to this fault model, contents of any w-bit memory word in a memory with n words, or ability tochange this contents, is influenced by the contents of any other s-1 words in the memory. A near optimal iterative method for construction of test patterns is proposed The systematic structure of the proposed test results in simple BIST implementations.