• Journal of Korea Game Society
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• v.14 no.6
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• pp.59-68
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• 2014

Memory bandwidth requirements of UHD (Ultra High Definition $4096{\times}2160$) game scenes have been much more increasing. This paper presents a lossless DPCM-GR based compression algorithm using CUDA for solving the memory bandwidth problem without sacrificing image quality, which is modified from DDPCM-GR [4] to support bit parallel pipelining. The memory bandwidth efficiency increases because of using the shared memory of CUDA. Various asynchronous transfer configurations which can overlap the kernel execution and data transfer between host and CUDA are implemented with the page-locked host memory. Experimental results show that the maximum 31.3 speedup is obtained according to CPU time. The maximum 30.3% decreases in the computation time among various configurations.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.240-240
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• 2010

A multiple alloy metal nano-dots memory using FN tunneling was investigated in order to confirm its structural possibility for future flash memory. In this work, a multiple FePt nano-dots device with a high work function (~5.2 eV) and extremely high dot density (${\sim}\;1.2{\times}10^{13}/cm^2$) was fabricated. Its structural effect for multiple layers was evaluated and compared to one with a single layer in terms of the cell characteristics and reliability. We confirm that MOS capacitor structures with 2-4 multiple FePt nano-dot layers provide a larger threshold voltage window and better retention characteristics. Furthermore, it was also revealed that several process parameters for block oxide and inter-tunnel oxide between the nano-dot layers are very important to improve the efficiency of electron injection into multiple nano-dots. From these results, it is expected that a multiple FePt nano-dots memory using Fowler-Nordheim (FN)-tunneling could be a candidate structure for future flash memory.

• The Journal of the Convergence on Culture Technology
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• v.7 no.1
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• pp.615-619
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• 2021

This study focuses on memory systems that are optimized to increase performance and energy efficiency in many embedded systems such as IoT, cloud computing, and edge computing, and proposes a performance improvement technique. The proposed technique improves memory system performance based on machine learning algorithms that are widely used in many applications. The machine learning technique can be used for various applications through supervised learning, and can be applied to a data classification task used in improving memory system performance. Data classification based on highly accurate machine learning techniques enables data to be appropriately arranged according to data usage patterns, thereby improving overall system performance.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.1
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• pp.23-28
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• 2023

This paper demonstrates a novel NAND flash memory structure and annealing configuration including through-silicon via (TSV) inside the silicon substrate to improve annealing efficiency using an electro-thermal annealing (ETA) technique. Compared with the conventional ETA which utilizes WL-to-WL current flow, the proposed annealing method has a higher annealing temperature as well as more uniform heat distribution, because of thermal isolation on the silicon substrate. In addition, it was found that the annealing temperature is related to the electrical and thermal conductivity of the TSV materials. As a result, it is possible to improve the reliability of NAND flash memory. All the results are discussed based on 3-dimensional (3-D) simulations with the aid of the COMSOL simulator.

• Science of Emotion and Sensibility
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• v.14 no.1
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• pp.117-126
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• 2011

This study investigates the physical properties and manufacturing method of shape memory fabric for emotional garment made by polypropylene. For this purpose, polypropylene(PP) POY and SDY were texturized using low temperature and constant length heat treatment texturing technologies, respectively. The shape memory fabrics made using these texturized PP yarns were woven with two kinds of PET and PTT shape memory yarns on the air-jet loom and the various physical properties of four kinds of shape memory fabrics were measured and discussed. The tenacity and breaking strain of PP texturized yarns treated by low temperature and constant length heat treatment showed high weaving efficiency and the wet thermal shrinkage of PP textured yarns was shown less than 1.5%, dry thermal shrinkage was ranged between 3% and 5%, which means thermal stability compared to the PTT textured yarn with high thermal shrinkage, 5~8%. The shape memory characteristics of PP shape memory fabrics measured by Toray method showed five grade as same value as PTT shape memory fabric. The heat keeping property of the PP shape memory fabric showed 56% higher value than that of PTT shape memory fabric. The water repellency of PP shape memory fabric measured by spray method showed five grade as same value as PTT shape memory fabric treated with water repellent agent. Especially, shape memory properties of PP shape memory fabric measured by 3-D image and camera measurement methods showed similar characteristics to the PTT shape memory fabric.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1081-1090
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• 2013

In this paper, a C-band 10 W power amplifier with internally matched input and output matching circuit is designed and fabricated. The used power transistor for the power amplifier is GaAs pHEMT bare-chip. The wire bonding analysis considering the size of the capacitor and the position of transistor pad improves the accurate design. The matching circuit design with the package effect using EM simulation is performed. To reduce the unsymmetry of IMD3 in 2-tone measurement due to the memory effect, the bias circuit minimizing the memory effect is proposed and employed. The measured $P_{1dB}$, power gain, and power added efficiency are 39.8~40.4 dBm, 9.7~10.4 dB, and 33.4~38.0 %, respectively. Adopting the proposed bias circuit, the difference between the upper and lower IMD3 is less than 0.76 dB.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.4
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• pp.65-71
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• 2007

Doherty amplifier has more efficiency and distortion than general amplifier. These distortion classified amplitude distortion and phase distortion, memory effect distortion. This paper reports on an attempt to investigate, model and quantity the contribution of the electrical nonlinearity effects and the thermal memory effects to a doherty amplifier's distortion generation and suggests thermal memory effect compensator for pre-distorter. Also this paper reports on the development of an accurate dynamic expression of the instantaneous junction temperature as a function of the instantaneous dissipated power. The parameters of suggested model suppress thermal memory effects doherty amplifier with pre-distorter. Pre-distorter with electrothermal memory effect compensator for doherty amplifier enhanced ACLR performance about 22 dB than general doherty amplifier. Experiment results were mesured by 50W LDMOS Doherty amplifier and pre-distorter with electrothermal memory effect compensator was simulated by ADS.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.6
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• pp.1353-1360
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• 2016

We analyze the efficiency of the double-block-length hash functions, Abreast-DM, HIROSE, MDC-2, MJH, MJH-Double based on AES or LEA. We use optimized open-source code for AES, and our implemented source code for LEA. As a result, the hash functions based on LEA are generally more efficient than those, based on AES. In terms of speed, the hash function with LEA are 6%~19% faster than those with AES except for Abreast-DM. In terms of memory, the hash functions with LEA has 20~30 times more efficient than those with AES.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.31 no.1
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• pp.41-48
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• 2013

The aim of the present study is to design a memory-efficient octree for querying large 3D point cloud. The aim has been fulfilled by omitting variables for minimum bounding hexahedral (MBH) of each octree node expressed in C++ language and by passing the re-estimated MBH from parent nodes to child nodes. More efficiency has been reported by two-fold processes of generating pseudo and regular trees to declare an array for all anticipated nodes, instead of using new operator to declare each child node. Experiments were conducted by constructing tree structures and querying neighbor points out of real point cloud composed of more than 18 million points. Compared with conventional methods using MBH information defined in each node, the suggested methods have proved themselves, in spite of existing trade-off between speed and memory efficiency, to be more memory-efficient than the comparative ones and to be practical alternatives applicable to large 3D point cloud.

• The KIPS Transactions:PartA
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• v.10A no.6
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• pp.635-642
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• 2003

The radical development of recent network technology provides the basic foundation which can establish a high speed and cheap cluster system. It is a general trend that conventional cluster systems are built as the system over a fixed level based on stabilized and high speed local networks. A multi-distributed web cluster group is a web cluster model which can obtain high performance, high efficiency and high availability through mutual cooperative works between effective job division and system nodes through parallel performance of a given work and shared memory of SC-Server with low price and low speed system nodes on networks. For this, multi-distributed web cluster group builds a sub-cluster group bound with single imaginary networks of multiple system nodes and uses the web distributed shared memory of system nodes for the effective data transmission within sub-cluster groups. Since the presented model uses a load balancing and parallel computing method of large-scale work required from users, it can maximize the processing efficiency.