• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2009년도 정보 및 제어 심포지움 논문집
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• pp.240-242
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• 2009

Flash memories are one of best media to support future computer's storages. However, we need to improve traditional data management scheme due to the relatively slow characteristics of flash operation of SSD. Due to the unique characteristics of flash media and hard disk, the efficiency of I/O processing is severely reduced without special treatment, especially in the presence of heavy workload or bulk data copy. In this respect, we need to design and develop efficient hybrid-RAID storage system.

• 전기의세계
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• 제26권1호
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• pp.77-81
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• 1977

This paper aims to develope a new algorithm to overcome the disadvantages of the conventional E.L.D system based on the B-Constants and Penalty-Factors scheme. The main features of this paper are that the Variabiable Decoupled Method usually employed in the Load-Flow studies is introduced to the E.L.D. algorithm developed by Sasson, using the Powell's Nonlinear Programming Scheme. Besides this, other minor refinements are made to reduce memory spaces and computing time. Case studies show that the method suggested here has the remarkable advantages of computing efficiency and memory requirements over Sasson's.

• 한국통신학회논문지
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• 제5권1호
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• pp.60-69
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• 1980

크고 複雜한 線形回路方程式을 갖는 큰 계통의 回路를 解析하기 위해서는 매우 많은 記憶容量과 時間이 必要하다. 이러한 記憶容量과 계산 時間을 줄이기 위해서 본 論文에서는 Sparse 行列을 利用하여 增幅回路의 最適 設計를 하였다.

• Journal of information and communication convergence engineering
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• 제6권1호
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• pp.47-50
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• 2008

A novel high channel efficiency transceiver based on a fast acquisition frequency synthesizer has been designed. The direct digital synthesis (DDS) technique is applied and a simple memory look-up table is incorporated to expedite channel acquisition. The technique simplifies the frequency control process in the transceiver and thus reduces the channel switching time. As a result, the channel efficiency is improved. The designed transceiver is ideal for frequency hopping mobile communication applications.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.473-476
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• 2004

AS supply voltage of DRAM is scaled down, voltage circuit that is stable from external noise is more important. $V_{PP}$ voltage is very important, it is biased to gate of memory cell transistor and possible to read and write without voltage down. It has both high pump gain and high power efficiency therefore charge pump circuit is proposed. The circuit is simulated by 0.18${\mu}m$ memory process and 1.2V supply voltage. Compare to CCTS, it is improved 0.43V of pump gain, $3.06\%$ of power efficiency at 6 stage.

• 대한기계학회논문집B
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• 제26권11호
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• pp.1521-1530
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• 2002

This article proposes a pressure based method for predicting flows at all speeds. The compressible SIMPLE algorithm is extended to unstructured grid framework. Convection terms are discretized using second-order scheme with deferred correction approach. Diffusion term discretization is based on structured grid analogy that can be easily adopted to hybrid unstructured grid solver. This method also uses node centered scheme with edge based data structure for memory and computing time efficiency of arbitrary grid types. Both incompressible and compressible benchmark problems are solved using the above methodology. The demonstration of this method is extended to slip flow problem that has low Reynolds number but compressibility effect. It is shown that the proposed method can improve efficiency in memory usage and computing time without losing any accuracy.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2008년도 추계학술대회A
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• pp.1427-1432
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• 2008

This paper describes the locomotion of a water jumping robot which attempts to emulate the fishing spider’s ability to jump on the water surface. While previous studies of the robots mimicking arthropods living on water were focused on recreating their horizontal skating motions, here we aim to achieve a vertical jumping motion. The robot jumps by pushing the water surface with rapidly released legs which were initially bent. The motion is triggered with a latch driven by the shape memory alloy actuator. The robot is capable of jumping to the maximum height of 26mm. Jumping efficiency, defined the maximum jumping height on water over the maximum jumping height on rigid ground, is 0.26 This work represents a first step toward robots that can locomote on water with superior versatility including skating and jumping.

• 한국자동차공학회논문집
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• 제8권3호
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• pp.151-162
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• 2000

This study is concerned with computerized multi-level substructuring methods and stress analysis of coil springs. The purpose of substructuring methods is to reduce computing time and capacity of computer memory by multiple level reduction of the degrees of freedom in large size problems that are modeled by three dimensional continuum finite elements. In this paper, the spring super element developed is investigated with tension, torsion, and bending of a cylindrical bar in order to verify its accuracy and efficiency for the multi-level substructuring method. And then the algorithm is applied to finite element analysis of coil springs. The result demonstrates the validity of the multi-level substructuring method and the efficiency in computing time and memory by providing good computational results in coil spring analysis.

• Computers and Concrete
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• 제23권5호
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• pp.311-320
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• 2019

The substructuring technique is one of the efficient methods for reducing computational effort and memory usage in the finite element method, especially in large-scale structures. Proper mesh partitioning plays a key role in the efficiency of the technique. In this study, new algorithms are proposed for mesh partitioning based on an element search technique. The computational cost function is optimized by aligning each element of the structure to a proper substructure. The genetic algorithm is employed to minimize the boundary nodes of the substructures. Since the boundary nodes have a vital performance on the mesh partitioning, different strategies are proposed for the few number of substructures and higher number ones. The mesh partitioning is optimized considering both computational and memory requirements. The efficiency and robustness of the proposed algorithms is demonstrated in numerous examples for different size of substructures.

• 한국정보처리학회논문지
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• 제7권7호
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• pp.2204-2218
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• 2000

This paper proposes a dynamic storage allocation algorithm, QHF(quick-half-fit) for real-time systems. The proposed algorithm manages a free block list per each worked size for memory requests of small size, and a free block list per each power of 2 size for memory requests of large size. This algorithms uses the exact-fit policy for small sie requests and provides high memory utilization. The proposed algorithm also has the time complexity O(I) and enables us to easily estimate the worst case execution time (WCET). In order to confirm efficiency of the proposed algorithm, we compare he memory utilization of proposed algorithm with that of half-fit and binary buddy system that have also time complexity O(I). The simulation result shows that the proposed algorithm guarantees the constant WCET regardless of the system memory size and provides lower fragmentation ratio and allocation failure ratio thant other two algorithms.