• Proceedings of the KIEE Conference
• /
• 1992.07a
• /
• pp.365-368
• /
• 1992

This paper presents an approach to the design of real time task scheduling for a line controller of continuous manufacturing process automation. The line controller has multiprocessor-based architecture with shared memory and is operated by firmware. This firmware contains menu-driven software supporting real-time database management and fuction-block control language. The multitasking line control processor performs the following three functions: 1) interprets the function block control language by virtue of shared memory in the database; 2) invokes an interupt service routine as required by external hardware; 3) detects errors and notifies the user. We propose real time task scheduling method.

• Journal of Institute of Control, Robotics and Systems
• /
• v.18 no.6
• /
• pp.519-525
• /
• 2012

Electric brake booster systems replace conventional pneumatic brake boosters with electric motors and rotary-todisplacement mechanisms including ECU (Electronic Control Unit). Electric booster brake systems require precise target pressure tracking and control robustness because vehicle brake systems operate properly given the large range of loading and temperature, actuator saturation, load-dependent friction. Also for the implement of imbedded control system, the controller should be selected considering the limited memory size and the cycle time problem of real brake ECU. In this study, based on these requirements, a sliding mode controller has been chosen and applied considering both model uncertainty and external disturbance. A mathematical model for the electric booster is derived and simulated. The developed sliding mode controller considering chattering problem has been compared with a conventional cascade PID controller. The effectiveness of the controller is demonstrated in some braking cases.

• Journal of IKEEE
• /
• v.4 no.2 s.7
• /
• pp.212-224
• /
• 2000

In this paper, a parallel processing system is proposed for improving the processing speed of image related applications. The proposed parallel processing system is fully synchronous SIMD computer with pipelined architecture and consists of processing elements and a multi-access memory system. The multi-access memory system is made up of memory modules and a memory controller, which consists of memory module selection module, data routing module, and address calculating and routing module, to perform parallel memory accesses with the variety of types: block, horizontal, and vertical access way. Morphological filter had been applied to verify the parallel processing system and resulted in faithful processing speed.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 2002.05a
• /
• pp.175-178
• /
• 2002

The proposed immune algorithm has an uncomplicated structure and memory-cell mechanism as the optimization algorithm which imitates the principle of humoral immune response, and has been used as methods to solve parameter optimization problems. Up to now, the applications of immune algorithm have been optimization problems with non-varying system parameters. Therefore, the effect of memory-cell mechanism, which is a merit of immune algorithm, is without. this paper proposes the immune algorithm using a memory-cell mechanism which can be the application of system with nonlinear varying parameters. To verified performance of the proposed immune algorithm, the speed control of nonlinear DC motor are performed. Computer simulation studies show that the proposed immune algorithm has a fast convergence speed and a good control performances under the varying system parameters.

• Proceedings of the KIEE Conference
• /
• 2006.07d
• /
• pp.2249-2250
• /
• 2006

기존의 89S51의 Flash Memory에 데이터를 저장하기 위해서 패러럴 포트를 사용하였다. 하지만 패러럴 포트를 이용한 방법은 많은 단점을 갖고 있는데, 그 중에 하나의 포트에 하나의 디바이스밖에 접속 할 수 없기 때문에 여러 디바이스를 접속하기 위해서는 포트 수를 증가시켜야 한다는 문제점이 있다. PC는 패러럴 포트를 $1^{\sim}2$개 정도만 갖고 있어서 확장을 하기가 여의치 않다. 이에 따라 패러럴 포트의 단점을 보완하고자 한다. 이러한 문제를 해결하고 보완 할 수 있는 USB 통신을 이용해 Micro-Controller인 89S51에 내장된 Flash Memory에 데이터를 저장 하려고 한다.

• Proceedings of the KIEE Conference
• /
• 2006.07a
• /
• pp.617-618
• /
• 2006

기존의 89S51의 Flash Memory에 데이터를 저장하기 위해서 패러럴 포트를 사용하였다. 하지만 패러럴 포트를 이용한 방법은 많은 단점을 갖고 있는데, 그 중에 하나의 포트에 하나의 디바이스밖에 접속 할 수 없기 때문에 여러 디바이스를 접속하기 위해서는 포트 수를 증가시켜야 한다는 문제점이 있다. PC는 패러럴 포트를 1개 정도만 갖고 있어서 화장을 하기가 여의치 않다. 이에 따라 패러럴 포트의 단점을 보완하고자 한다. 이러한 문제를 해결하고 보완 할 수 있는 USB 통신을 이용해 Micro-Controller인 89S51에 내장된 Flash Memory에 데이터를 저장하려고 한다.

• Proceedings of the KIEE Conference
• /
• 1989.11a
• /
• pp.488-493
• /
• 1989

In this paper, the structure of CMAC address mapping is first revisited, and the address hashing function and the random mapping is discussed in the conventional CMAC implementation. Then the effective size of CMAC memory is derived from the modulus property of the CMAC address vector, and a new hashing function for the effective memory mapping is proposed for a CMAC implementation with feasible memory size and no troublesome random mapping. Finally, the performance of the conventional CMAC learning algorithm and that of the proposed new CMAC scheme arc compared via simulations.

• Information and Communications Magazine
• /
• v.25 no.12
• /
• pp.10-18
• /
• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• Proceedings of the KIEE Conference
• /
• 2006.07b
• /
• pp.1283-1284
• /
• 2006

기존의 89S51의 Flash Memory에 데이터를 저장하기 위해서 패러럴 포트를 사용하였다. 하지만 패러럴 포트를 이용한 방법은 많은 단점을 갖고 있는데, 그 중에 하나의 포트에 하나의 디바이스밖에 접속 할 수 없기 때문에 여러 디바이스를 접속하기 위해서는 포트 수를 증가시켜야 한다는 문제점이 있다. PC는 패러럴 포트를 $1{\sim}2$개 정도만 갖고 있어서 확장을 하기가 여의치 않다. 이에 따라 패러럴 포트의 단점을 보완하고자 한다. 이러한 문제를 해결하고 보완 할 수 있는 USB 통신을 이용해 Micro-Controller인 89S51에 내장된 Flash Memory에 데이터를 저장 하려고 한다.

• Proceedings of the IEEK Conference
• /
• 2002.07c
• /
• pp.1571-1574
• /
• 2002

This paper describes a circuit and its operations of a programmable digital on-chip terminator designed with CMOS circuits which are used in high speed I/O interface. The on-chip terminator matches external reference resistor with the accuracy of ${\pm}$ 4.1％ over process, voltage and temperature variation. The digital impedance codes are generated in programmable impedance controller (PIC), and the codes are sent to terminator transistor arrays at input pads serially to reduce the number of signal lines. The transistor array is thermometer-coded to reduce impedance glitches during code update and it is segmented to two different blocks of thermometer-coded transistor arrays to reduce the number of transistors. The terminator impedance is periodically updated during hold time to minimize inter-symbol interferences.