• Phonetics and Speech Sciences
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• v.3 no.4
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• pp.95-102
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• 2011

The purpose of this study was to identify the characteristics of the phonological discrimination ability and phonological working memory of 10 typically developing children aged 4, and 10 other children with Specific Language Impairments whose language age is similar. In orders to compare their phonological discrimination ability among phonological awareness, discrimination tasks were conducted at the syllable and phoneme levels. Also, in order to compare their phonological working memory, the subjects repeated nonsense syllables. The research results may be summarized as follows: First, the children with Specific Language Impairments demonstrated a lower performance than the typically developing children in phonological discrimination ability at both syllable and phoneme levels, and the difference between the groups was statistically significant. Second, the children with Specific Language Impairments exhibited a lower phonological working memory performance in all syllables compared with normal children. Although there was no significant difference in 2 and 3 syllables, a significant difference appeared as the length of the syllables became longer from 4 to 6 syllables. It is deemed necessary to conduct research into qualitative and quantitative differences through an formal assessment of the phonological awareness and phonological working memory of children with Specific Language Impairments.

• ETRI Journal
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• v.30 no.6
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.68-76
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• 2015

Phase-change memory (PCM) is a promising technology that is anticipated to be used in the memory hierarchy of future computer systems. However, its access time is relatively slower than DRAM and it has limited endurance cycle. Due to this reason, PCM is being considered as a high-speed storage medium (like swap device) or long-latency memory. In this paper, we adopt PCM as a virtual memory swap device and present a new page replacement policy that considers the characteristics of PCM. Specifically, we aim to reduce the write traffic to PCM by considering the dirtiness of pages when making a replacement decision. The proposed replacement policy tracks the dirtiness of a page at the granularity of a sub-page and replaces the least dirty page among pages not recently used. Experimental results with various workloads show that the proposed policy reduces the amount of data written to PCM by 22.9% on average and up to 73.7% compared to CLOCK. It also extends the lifespan of PCM by 49.0% and reduces the energy consumption of PCM by 3.0% on average.

• Smart Structures and Systems
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• v.4 no.3
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• pp.367-389
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• 2008

Shape Memory Alloys (SMAs) are unique materials with a paramount potential for various applications in bridges. The novelty of this material lies in its ability to undergo large deformations and return to its undeformed shape through stress removal (superelasticity) or heating (shape memory effect). In particular, Ni-Ti alloys have distinct thermomechanical properties including superelasticity, shape memory effect, and hysteretic damping. SMA along with sensing devices can be effectively used to construct smart Reinforced Concrete (RC) bridges that can detect and repair damage, and adapt to changes in the loading conditions. SMA can also be used to retrofit existing deficient bridges. This includes the use of external post-tensioning, dampers, isolators and/or restrainers. This paper critically examines the fundamental characteristics of SMA and available sensing devices emphasizing the factors that control their properties. Existing SMA models are discussed and the application of one of the models to analyze a bridge pier is presented. SMA applications in the construction of smart bridge structures are discussed. Future trends and methods to achieve smart bridges are also proposed.

• KIISE Transactions on Computing Practices
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• v.23 no.3
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• pp.165-170
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• 2017

Many studies have utilized GPGPU (General-Purpose Graphic Processing Unit) and its high computing power to compute complex tasks. The characteristics of GPGPU programs necessitate the operations of memory copy between the host and device. A high latency period can affect the performance of the program. Thus, it is required to significantly improve the performance of GPGPU programs by optimizations. By executing multiple GPGPU programs simultaneously, the latency hiding effect of memory copy is achieved by overlapping the memory copy and computing operations in GPGPU. This paper presents the results of analyzing the latency hiding effect for memory copy operations. Furthermore, we propose a performance anticipation model and an algorithm for the limitations of using pinned memory, and show that the use of the proposed algorithm results in a 41% performance increase.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.28.2-28.2
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• 2011

Resistance random access memory (ReRAM) is a promising candidate for next-generation nonvolatile memory because of its advantageous qualities such as simple structure, superior scalability, fast switching speed, low-power operation, and nondestructive readout. We investigated the resistive switching behavior of tantalum oxide that has been widely used in dynamic random access memories (DRAM) in the present semiconductor industry. As a result, it possesses full compatibility with the entrenched complementary metal-oxide-semiconductor processes. According to previous studies, TiN is a good oxygen reservoir. The TiN top electrode possesses the specific properties to control and modulate oxygen ion reproductively, which results in excellent resistive switching characteristics. This study presents fully room temperature fabricated the TiN/$TaO_x$/Pt devices and their electrical properties for nonvolatile memory application. In addition, we investigated the TiN electrode dependence of the electrical properties in $TaO_x$ memory devices. The devices exhibited a low operation voltage of 0.6 V as well as good endurance up to $10^5$ cycles. Moreover, the benefits of high devise yield multilevel storage possibility make them promising in the next generation nonvolatile memory applications.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.4
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• pp.143-148
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• 2017

Flash Memory which is light and strong external shock as storage of small electronics like smartphone, digital camera, car black box has been widely used. Since the operation speed of the read operation and the write operation are different from each other, and the flash memory has the feature that it is not possible to overwrite, the delete operation is added to solve these problems. Wear-leveling must also be considered, since the number of erase times of the flash memory is limited. Many studies have been conducted on the substitutional algorithms of flash memory based on these characteristics of recent flash memories. So, to solve the problem that has existing buffer replacement algorithm this thesis divide page into 6 groups and when proposed algorithm select victim page, it consider reference page frequency and page recency.

• BMB Reports
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• v.49 no.4
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• pp.199-200
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• 2016

Gene regulation in the brain is essential for long-term plasticity and memory formation. Despite this established notion, the quantitative translational map in the brain during memory formation has not been reported. To systematically probe the changes in protein synthesis during memory formation, our recent study exploited ribosome profiling using the mouse hippocampal tissues at multiple time points after a learning event. Analysis of the resulting database revealed novel types of gene regulation after learning. First, the translation of a group of genes was rapidly suppressed without change in mRNA levels. At later time points, the expression of another group of genes was downregulated through reduction in mRNA levels. This reduction was predicted to be downstream of inhibition of ESR1 (Estrogen Receptor 1) signaling. Overexpressing Nrsn1, one of the genes whose translation was suppressed, or activating ESR1 by injecting an agonist interfered with memory formation, suggesting the functional importance of these findings. Moreover, the translation of genes encoding the translational machineries was found to be suppressed, among other genes in the mouse hippocampus. Together, this unbiased approach has revealed previously unidentified characteristics of gene regulation in the brain and highlighted the importance of repressive controls.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.9-9
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• 2011

There has been strong demand for novel nonvolatile memory technology for low-cost, large-area, and low-power flexible electronics applications. Resistive memories based on metal oxide thin films have been extensively studied for application as next-generation nonvolatile memory devices. However, although the metal oxide-based resistive memories have several advantages, such as good scalability, low-power consumption, and fast switching speed, their application to large-area flexible substrates has been limited due to their material characteristics and necessity of a high-temperature fabrication process. As a promising nonvolatile memory technology for large-area flexible applications, we present a graphene oxide-based memory that can be easily fabricated using a room temperature spin-casting method on flexible substrates and has reliable memory performance in terms of retention and endurance. The microscopic origin of the bipolar resistive switching behaviour was elucidated and is attributed to rupture and formation of conducting filaments at the top amorphous interface layer formed between the graphene oxide film and the top Al metal electrode, via high-resolution transmission electron microscopy and in situ x-ray photoemission spectroscopy. This work provides an important step for developing understanding of the fundamental physics of bipolar resistive switching in graphene oxide films, for the application to future flexible electronics.

• Industrial Engineering and Management Systems
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• v.9 no.3
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• pp.227-241
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• 2010

A memory module industry's supply chain usually consists of multiple manufacturing sites and multiple distribution centers. In order to fulfill the variety of demands from downstream customers, production planners need not only to decide the order allocation among multiple manufacturing sites but also to consider memory module industrial characteristics and supply chain constraints, such as multiple material substitution relationships, capacity, and transportation lead time, fluctuation of component purchasing prices and available supply quantities of critical materials (e.g., DRAM, chip), based on human experience. In this research, a directed graph-based supply network planning (DGSNP) model is developed for memory module industry. In addition to multi-site order allocation, the DGSNP model explicitly considers production planning for each manufacturing site, and purchasing planning from each supplier. First, the research formulates the supply network's structure and constraints in a directed-graph form. Then, a proposed genetic algorithm (GA) solves the matrix form which is transformed from the directed-graph model. Finally, the final matrix, with a calculated maximum profit, can be transformed back to a directed-graph based supply network plan as a reference for planners. The results of the illustrative experiments show that the DGSNP model, compared to current memory module industry practices, determines a convincing supply network planning solution, as measured by total profit.