• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9B
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• pp.1305-1313
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• 2010

Last few years, wireless personal area network (WPAN) has been widely researched for various healthcare applications. Due to restriction of device hardware (e.g., energy and memory), we need to design a highly-versatile MAC layer protocol for WBAN (Wireless Body Area Network). In addition, when an emergency occurs to a patient, a priority mechanism is necessitated for a urgent message to get through to the final destination. This paper presents a priority mechanism referred to as hybrid priority MAC for WBAN. Through extensive simulation, we show the proposed MAC protocol can minimize the average packet latency for urgent data. Thus, when patients have an emergency situation, our MAC allows adequate assistance time and medical treatment for patients. The simulation based on NS-2 shows that our Hybrid Priority MAC has the good performance and usability.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.8-22
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• 2014

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.6
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• pp.58-64
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• 2009

For the success of the reconfigurable computing, the algorithm for mapping operations onto coarse-grained reconfigurable architecture is very important. This paper proposes a resource-aware mapping system for the coarse-grained reconfigurable architecture and its own underlying heuristic algorithm. The operation assignment and the routing path allocation are simultaneously performed with a cycle-accurate time-exclusive resource model. The proposed algorithm minimizes the communication resource usage and the global memory access with the list scheduling heuristic. The operation to be mapped are prioritized with general properties of data flow. The evaluations of the proposed algorithm show that the performance is significantly enhanced in several benchmark applications.

• Journal of KIISE:Databases
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• v.28 no.3
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• pp.334-343
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• 2001

Most of currently used videos have variable bit rate(VBR) characteristics. Since the display rate of VBR videos compared to CBR videos vary with time, it is not proper to configure resources of the VBR video server using the method proposed for the CBR video server. In this paper we propose an optimal resource configuration method for the VBR video server which is based on the probability model. The proposed method decides the amount of disk and memory, and the disk access cycle of the video server with the lowest hardware cost, while preserving the throughput of the video server. In addition, we show the usefulness of the method through the various experiments.

• Proceedings of the Korean Vacuum Society Conference
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• 2000.02a
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• pp.69-69
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• 2000

(Ba, Sr)TiO3 (BST)[1-3] 박막은 유전상수가 크고 고주파에서도 유전특성 저하가 적기 때문에 ULSI DRAM(Dynamic Random Access Memory)에 응용 가능한 물질로 최근 각광을 받고 있다. 하지만, 아직 BST 박막을 DRSM에 바로 적용하기 위해선 몇 가지 문제점이 있다. 그 중 누설전류 문제는 디바이스 응용시 매우 중요한 요소이다. 특히, DRAM에서 refresh time와 직접적인 관련이 있어 디바이스 내의 신뢰도 및 전력소모를 결정하는 주된 인자가 된다. 지금까지, BST 박막의 인가전업, 온도, 그리고 전극물질에 따른 누설전류 현상들이 고찰되었고, 이에 관한 많은 전도기구 모델들이 제시되었다. Schottky emission, Poole-Frenkel emission, space charge limited conduction 등이 그 대표적인 예이다. 하지만 아쉽게도 BST 박막의 정확한 누설 전류 전도 기구를 완전히 설명하는데는 아직 한계가 있다. 따라서 본 연구에서는 제작된 BST 커패시터 내의 기본적인 전기적 성질을 조사하고, 정확한 누설전류 기구 규명에 초점을 두고자 한다. 이를 위해 기존의 여러 기구들과 비교 분석할 것이다. 하부전극으로 사용하기 위해 스퍼터링 방법으로 p-Si(100) 기판위에 RuO2 박막을 약 120nm 증착하였다. 증착전의 chamberso의 초기압력은 5$\times$10-6 Torr이하의 압력으로 유지시켰다. Ar/O2의 비는 이전 실험에서 최적화된 9/1로 하였다. BST 박막 증착 시 5분간 pre-sputtering을 실시한 후 하부전극 기판위에 BST 박막을 증착하였다. 증착이 끝난 후 시편을 상온까지 냉각시킨 후 꺼내었다. 전기적 특성을 측정하기 상부전극으로 RuO2와 Al 박막을 각각 상온에서 100nm 증착하였다. 이때 hole mask를 이용하여 반경이 140um인 원형의 상부전극을 증착하였다. BST 박막의 증착온도가 증가하고 Ar/O2 비가 감소할수록 제작된 BST-커패시터의 전기적 성질이 우수하였다. 증착온도 $600^{\circ}C$, ASr/O2=5/5에서 증착된 막의 누설전류는 4.56$\times$10-8 A/cm2, 유전상수는 600 정도의 값을 나타내었다. 인가전압에 따른 BST 커패시터의 transition-current는 Curie-von Schweider 모델을 따랐다. BST 박막의 누설전류 전도기구는 기존의 Schottky 모델이 아니라 modified-Schottky 무델로 잘 설명되었다. Modified-Schottky 모델을 통해 BST 박막의 광학적 유전율 $\varepsilon$$\infty$=4.9, 이동도 $\mu$=0.019 cm2/V-s, 장벽 높이 $\psi$b=0.79 eV를 구하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.6
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• pp.850-858
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• 2022

To deploy Gate Recurrent Units (GRU) on resource-constrained embedded devices, this paper presents a reconfigurable FPGA-based GRU accelerator that enables structured compression. Firstly, a dense GRU model is significantly reduced in size by hybrid quantization and structured top-k pruning. Secondly, the energy consumption on external memory access is greatly reduced by the proposed reuse computing pattern. Finally, the accelerator can handle a structured sparse model that benefits from the algorithm-hardware co-design workflows. Moreover, inference tasks can be flexibly performed using all functional dimensions, sequence length, and number of layers. Implemented on the Intel DE1-SoC FPGA, the proposed accelerator achieves 45.01 GOPs in a structured sparse GRU network without batching. Compared to the implementation of CPU and GPU, low-cost FPGA accelerator achieves 57 and 30x improvements in latency, 300 and 23.44x improvements in energy efficiency, respectively. Thus, the proposed accelerator is utilized as an early study of real-time embedded applications, demonstrating the potential for further development in the future.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.3
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• pp.355-366
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• 2022

This paper proposes a microcode-based neural network accelerator controller for artificial intelligence accelerators that can be reconstructed using a programmable architecture and provide the advantages of low-power and ultra-small chip size. In order for the target accelerator to support various neural network models, the neural network model can be converted into microcode through microcode compiler and mounted on accelerator to control the operators of the accelerator such as datapath and memory access. While the proposed controller and accelerator can run various CNN models, in this paper, we tested them using the YOLOv2-Tiny CNN model. Using a system clock of 200 MHz, the Controller and accelerator achieved an inference time of 137.9 ms/image for VOC 2012 dataset to detect object, 99.5ms/image for mask detection dataset to detect wearing mask. When implementing an accelerator equipped with the proposed controller as a silicon chip, the gate count is 618,388, which corresponds to 65.5% reduction in chip area compared with an accelerator employing a CPU-based controller (RISC-V).

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.17 no.5
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• pp.1396-1412
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• 2023

Conversation modeling is an important and challenging task in the field of natural language processing because it is a key component promoting the development of automated humanmachine conversation. Most recent research concerning conversation modeling focuses only on the current utterance (considered as the current question) to generate a response, and thus fails to capture the conversation's logic from its beginning. Some studies concatenate the current question with previous conversation sentences and use it as input for response generation. Another approach is to use an encoder to store all previous utterances. Each time a new question is encountered, the encoder is updated and used to generate the response. Our approach in this paper differs from previous studies in that we explicitly separate the encoding of the question from the encoding of its context. This results in different encoding models for the question and the context, capturing the specificity of each. In this way, we have access to the entire context when generating the response. To this end, we propose a deep neural network-based model, called the Context Model, to encode previous utterances' information and combine it with the current question. This approach satisfies the need for context information while keeping the different roles of the current question and its context separate while generating a response. We investigate two approaches for representing the context: Long short-term memory and Convolutional neural network. Experiments show that our Context Model outperforms a baseline model on both ConvAI2 Dataset and a collected dataset of conversational English.

• Journal of the Korea Society of Computer and Information
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• v.18 no.11
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• pp.1-12
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• 2013

In multi-core processors, Last Level Cache(LLC) can reduce the speed gap between the memory and the core. For this reason, LLC has big impact on the performance of processors. LLC is composed of shared cache and private cache. In computer architecture community, most researchers have mainly focused on the management techniques for shared cache, while management techniques for private cache have not been widely researched. In conventional private LLC, memory is statically assigned to each core, resulting in serious performance degradation when the workloads are not fairly distributed. To overcome this problem, this paper proposes the replacement policy for managing private cache of LLC efficiently. As proposed core-aware cache replacement policy can reconfigure LLC dynamically, hit rate of LLC is increases drastically. Moreover, proposed policy uses 2-bit saturating counters to improve the performance. According to our simulation results, the proposed method can improve hit rates by 9.23% and reduce the access time by 12.85% compared to the conventional method.

• Korean Journal of Optics and Photonics
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• v.18 no.5
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• pp.351-361
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• 2007

The samples composed of a GST thin film and the protective layers of $ZnS-SiO_2$ or $Al_2O_3$ coated on c-Si substrate were prepared by using the magnetron sputtering method. Samples of three different structures were prepared, that is, i) the GST single film on c-Si substrate, ii) the GST film sandwiched by the protective $ZnS-SiO_2$ layers on c-Si substrate, and iii) the GST film sandwiched by $Al_2O_3$ protective layers on c-Si substrate. The ellipsometric constants in the temperature range from room temperature to $700^{\circ}C$ were obtained by using the in-situ ellipsometer equipped with a conventional heating chamber. The measured ellipsometric constants show strong variations versus temperature. The variation of ellipsometric constants at the temperature region higher than $300^{\circ}C$ shows different behaviors as the ambient medium is changed from in air to in vacuum or the protective layers are changed from $ZnS-SiO_2$ to $Al_2O_3$. Since the long heating time of 1-2 hours is believed to be the origin of the high temperature variation of ellipsometric constants upon the heating environment and the protective layers, a PRAM (Phase-Change Random Access Memory) recorder is introduced to reduce the heating time drastically. By using the PRAM recorder, the GST samples are heated up to $700^{\circ}C$ decomposed preventing its partial evaporation or chemical reactions with adjacent protective layers. The surface image obtained by SEM and the surface micro-roughness verified by AFM also confirmed that samples prepared by the PRAM recorder have smoother surface than the samples prepared by using the conventional heater.