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A Resource-Aware Mapping Algorithm for Coarse-Grained Reconfigurable Architecture Using List Scheduling  

Kim, Hyun-Jin (Department of Electrical and Electronic Engineering, Yonsei University)
Hong, Hye-Jeong (Department of Electrical and Electronic Engineering, Yonsei University)
Kim, Hong-Sik (Department of Electrical and Electronic Engineering, Yonsei University)
Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.46, no.6, 2009 , pp. 58-64 More about this Journal
Abstract
For the success of the reconfigurable computing, the algorithm for mapping operations onto coarse-grained reconfigurable architecture is very important. This paper proposes a resource-aware mapping system for the coarse-grained reconfigurable architecture and its own underlying heuristic algorithm. The operation assignment and the routing path allocation are simultaneously performed with a cycle-accurate time-exclusive resource model. The proposed algorithm minimizes the communication resource usage and the global memory access with the list scheduling heuristic. The operation to be mapped are prioritized with general properties of data flow. The evaluations of the proposed algorithm show that the performance is significantly enhanced in several benchmark applications.
Keywords
Reconfigurable architecture; Instruction mapping; List scheduling;
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