• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1031-1038
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• 2005

In this paper, we propose real-time 3D image converting architecture by a unit of pixel for 2D/3D compatible PC and LCD of cellular phone with parallax burier, and implement a system for overall display operation after designing a circuit based on FPGA. After digitizing anolog image signal from PC, we recompose it to 3D image signal according to input image type. Since the architecture which rearranges 2D image to 3D depends on parallax burier, we use interleaving method which mixes pixels by a unit of R, G, and B cell. The propose architecture is designed into a circuit based on FPGA with high-speed memory access technique and use 4 SDRAMs for high performance data storing and processing. The implemented system consists of A/D converting system, FPGA system to formatting 2D signal to 3D, and LCD panel with parallax barrier, for 3D display.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.56-56
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• 2011

투명 메모리 소자는 향후 투명 디스플레이 등 투명 전자기기와 집적화해 통합형 투명 전자시스템을 구현을 위해 지속적으로 연구가 진행 되고 있으며, 산학계에서는 다양한 메모리 소자중 큰 밴드-갭(>3 eV) 특성을 가지는 저항 변화 메모리(Resistive Random Access Memory, ReRAM)를 이용한 투명 메모리 구현 가능성을 지속적으로 보고하고 있다. 현재까지의 저항 변화 메모리 연구는 물질 최적화를 위해 다양한 금속-산화물계(Metal-Oxide) 저항 변화 물질에 대한 연구가 활발하게 진행 되고 있지만, 금속-산화물계 물질의 경우 근본 적으로 그 제조 공정상 산소에 의한 다수의 산소 디펙트 형성과 제작 시 쉽게 발생할 수 있는 표면 오염의 문제점을 안고 있으며, 또한 Endurance 및 Retention 등의 신뢰성에 문제를 보이고 있다. 따라서, 이러한 문제점을 근본 적으로 해결하기 위해 새로운 저항 변화 물질에 관한 물질 최적화 연구가 요구 되며, 본 연구진은 다양한 금속-질화물계(Metal-Nitride) 물질을 저항변화 물질로 제안해 연구를 진행 하고 있다. 이전 연구에서, 물질 고유의 우수한 열전도(285 W/($m{\cdot}K$)) 및 절연 특성, 큰 밴드-갭(6.2 eV), 높은 유전율(9)을 가지고 있는 금속-질화물계 박막인 AlN를 저항변화 물질로 이용하여 저항변화 메모리 소자 연구를 진행하였으며, 저전압 고속 동작 특성을 보이는 신뢰성 있는 저항 변화 메모리를 구현하였다. 본 연구에서는 AlN의 큰 밴드-갭 특성을 이용하여 투명 메모리 소자를 구현하기 위한 연구를 진행 하였다. 투과도 실험 결과, 가시광 영역 (380-700 nm)에서 80% 이상의 투과도를 보였으며, 이는 투명 메모리 소자로써의 충분한 가능성을 보여 준다. 또한, I-V 실험에서 전형적인 bipolar 스위칭 특성을 보이며, 스위칭 전압 및 속도는 VSET=3 V/Time=10 ns, VRESET=-2 V/Time=10ns에서 가능하였다. 신뢰성 실험에서, 108번의 endurance 특성 및 105 초의 retention 특성을 보였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.132-132
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• 2011

For the programming volume of PRAM, Ge2Sb2Te5(GST) thin films have been dominantly used and prepared by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD). Among these methods, ALD is particularly considered as the most promising technique for the integration of PRAM because the ALD offers a superior conformality to PVD and CVD methods and a digital thickness control precisely to the atomic level since the film is deposited one atomic layer at a time. Meanwhile, although the IST has been already known as an optical data storage material, recently, it is known that the IST benefits multistate switching behavior, meaning that the IST-PRAM can be used for mutli-level coding, which is quite different and unique performance compared with the GST-PRAM. Therefore, it is necessary to investigate a possibility of the IST materials for the application of PRAM. So far there are many attempts to deposit the IST with MOCVD and PVD. However, it has not been reported that the IST can be deposited with the ALD method since the ALD reaction mechanism of metal organic precursors and the deposition parameters related with the ALD window are rarely known. Therefore, the main aim of this work is to demonstrate the ALD process for IST films with various precursors and the conformal filling of a nano size programming volume structure with the ALD?IST film for the integration. InSbTe (IST) thin films were deposited by ALD method with different precursors and deposition parameters and demonstrated conformal filling of the nano size programmable volume of cell structure for the integration of phase change random access memory (PRAM). The deposition rate and incubation time are 1.98 A/cycle and 25 cycle, respectively. The complete filling of nano size volume will be useful to fabricate the bottom contact type PRAM.

• Journal of Korea Society of Industrial Information Systems
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• v.15 no.2
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• pp.31-39
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• 2010

VoD(Video-on-Demand) servers have to provide timely processing guarantees for continuous media and reduce the storage and bandwidth requirements for continuous media. The compression techniques make the bit rates of compressed video data significantly variable from frame to frame. A VoD system should be able to provide the client with interactive operations such as fast forward and fast rewind in addition to normal playback of movie. However, interactive operations require additional resources such as storage space, disk bandwidth, memory and network bandwidth. In a stored video application such as VoD system, it is possible that a priori disk access patterns can be used to reserve the system resources in advance. In addition, clients of VoD server spend most of their time in playback mode and the period of time spent in interactive mode is relatively small. In this paper, I present the new buffer management scheme that provides efficient support for interactive operations in a VoD server using variable bit rate continuous media. Simulation results show that our strategy achieves 34% increase of the number of accepted clients over the LRU strategy.

• Journal of KIISE:Computing Practices and Letters
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• v.9 no.1
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• pp.13-24
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• 2003

MPEG-4 is a standard for multimedia applications and provides a set of technologies to satisfy the needs of authors, service providers and end users alike. In this paper, we suggest a Real-time Multiple Circular Buffer (M4RM Buffer) model, which is suitable for streaming these MPEG-4 contents efficiently. M4RM buffer generates each structure of the buffer, which matches well with each object composing an MPEG-4 content, according to the transferred information, and manipulates multiple read/write operations only by its reference. It divides the decoder buffer and the composition buffer, which are described in the standard, by the unit of frame allocated to minimize the range of access. This buffer unit of a frame is allocated according to the object description. Also, it processes the objects synchronization within the buffer and provides APIs for an efficient buffer management to process the real-time user events. Based on the performance evaluation, we show that M4RM buffer model decreases the waiting time in a buffer frame, and so allows the real-time streaming of an MPEG-4 content using the smaller size of the memory block than IM1-2D and Window Media Player.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.271-274
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• 2014

This paper proposes high-performance SAO(Sample Adaptive Offset) in HEVC(High Efficiency Video Coding) encoder for Ultra HD video processing in real time. SAO is a newly adopted technique belonging to the in-loop filter in HEVC. The proposed SAO encoder hardware architecture uses three-layered buffers to minimize memory access time and to simplify pixel processing and also uses only adder, subtractor, shift register and feed-back comparator to reduce area. Furthermore, the proposed architecture consists of pipelined pixel classification and applying SAO parameters, and also classifies four consecutive pixels into EO and BO concurrently. These result in the reduction of processing time and computation. The proposed SAO encoder architecture is designed by Verilog HDL, and implemented by 180k logic gates in TSMC $0.18{\mu}m$ process. At 110MHz, the proposed SAO encoder can support 4K Ultra HD video encoding at 30fps in real time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1B
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• pp.18-28
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• 2004

Efficient hardware implementation of address lookup is one of the most important design issues of internet routers. Address lookup significantly impacts router performance since routers need to process tens-to-hundred millions of packets per second in real time. In this paper, we propose a practical IP address lookup structure based on the binary tree of prefixes of different lengths. The proposed structure produces multiple balanced trees, and hence it solve the issues due to the unbalanced binary prefix tree of the existing scheme. The proposed structure is implemented using pipelined binary search combined with a small size TCAM. Performance evaluation results show that the proposed architecture requires a 2000-entry TCAM and total 245 kbyte SRAMs to store about 30,000 prefix samples from MAE-WEST router, and an address lookup is achieved by a single memory access. The proposed scheme scales very well with both of large databases and longer addresses as in IPv6.

• Journal of the Korea Society of Computer and Information
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• v.18 no.9
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• pp.11-19
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• 2013

Most modern computer systems employ cache systems in order to alleviate the access time gap between processor and memory system. The power dissipated by the cache systems becomes a significant part of the total power dissipated by whole microprocessor chip. Therefore, power reduction in the cache system becomes one of the important issues. Partial tag cache is the system for the least power consumption. The main power reduction for this method is due to the use of small partial tag matching, not full tag matching. In this paper, we first analyze the previous regular partial tag cache systems and propose a new address matching mechanism by using locality buffer and address compression. In simulation results, the proposed model shows 18% power reduction in average, still providing same performance level, compared to regular cache.

• ETRI Journal
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• v.42 no.4
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• pp.491-504
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• 2020

We present AB9, a neural processor for inference acceleration. AB9 consists of a systolic tensor core (STC) neural network accelerator designed to accelerate artificial intelligence applications by exploiting the data reuse and parallelism characteristics inherent in neural networks while providing fast access to large on-chip memory. Complementing the hardware is an intuitive and user-friendly development environment that includes a simulator and an implementation flow that provides a high degree of programmability with a short development time. Along with a 40-TFLOP STC that includes 32k arithmetic units and over 36 MB of on-chip SRAM, our baseline implementation of AB9 consists of a 1-GHz quad-core setup with other various industry-standard peripheral intellectual properties. The acceleration performance and power efficiency were evaluated using YOLOv2, and the results show that AB9 has superior performance and power efficiency to that of a general-purpose graphics processing unit implementation. AB9 has been taped out in the TSMC 28-nm process with a chip size of 17 × 23 ㎟. Delivery is expected later this year.

• Journal of Digital Contents Society
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• v.2 no.2
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• pp.103-115
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• 2001

This paper proposes the two algorithms which generate a minimal decision rule and approximate inference operation, adapted the rough set and the factor space theory in fuzzy knowledge base. The generation of the minimal decision rule is executed by the data classification technique and reduct applying the correlation analysis and the Bayesian theorem related attribute factors. To retrieve the specific object, this paper proposes the approximate inference method defining the membership function and the combination operation of t-norm in the minimal knowledge base composed of decision rule. We compare the suggested algorithms with the other retrieval theories such as possibility theory, factor space theory, Max-Min, Max-product and Max-average composition operations through the simulation generating the object numbers and the attribute values randomly as the memory size grows. With the result of the comparison, we prove that the suggested algorithm technique is faster than the previous ones to retrieve the object in access time.