• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.1
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• pp.88-97
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• 2000

We have proposed and analysed a novel Lookup Algorithm which had a short switching speed and tiny memory size for IP router. This algorithm could simply be implemeted by a hardware with SRAM because of simple structure. This Lookup scheme needs 1${\sim}$3 memory access times. When we simulated with 40,000 routing record obtained from IPMA Website, the maximum memory size of this algorithm was 316KB(the offset threshold for compression algorithm was 8). When we simulated by HDL using ALTERA EPM7256 series and 100MHz clock and SRAM of 10ns access time, the total lookup time was 45ns for two memory access, 175ns for three memory access.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4C
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• pp.349-354
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• 2009

In this paper, a new motion compensation scheme to reduce external memory access frequency which is one of the major bottlenecks for real-time decoding is proposed. Most H.264/AVC decoders store reference pictures in external memories due to the large size and reference blocks are read into the decoder core as needed during decoding. If the reference data access is done for each reference block in decoding sequence, the memory bandwidth can be unacceptable for real-time decoding. This paper presents a memory access scheme for motion compensation to read as many reference data as possible with reduced memory access frequency by analyzing reference data access pattern for each macroblock. Experimental results show that the proposed motion compensation scheme leads to approximately 30% improvement in memory bandwidth requirement.

• Journal of Computing Science and Engineering
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• v.8 no.2
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• pp.78-86
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• 2014

Aiming to solve the problems of high memory access and big storage space and long matching time in the regular expression matching of extended finite automaton (XFA), a new regular expression matching algorithm based on high-efficient finite automaton is presented in this paper. The basic idea of the new algorithm is that some extra judging instruments are added at the starting state in order to reduce any unnecessary transition paths as well as to eliminate any unnecessary state transitions. Consequently, the problems of high memory access consumption and big storage space and long matching time during the regular expression matching process of XFA can be efficiently improved. The simulation results convey that our proposed scheme can lower approximately 40% memory access, save about 45% storage space consumption, and reduce about 12% matching time during the same regular expression matching process compared with XFA, but without degrading the matching quality.

• Journal of Korea Multimedia Society
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• v.14 no.11
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• pp.1401-1408
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• 2011

This dissertation present a chip with Multi-Access Memory System(MAMS) and parallel processor for 16 Processing Elements of image processing purpose. MAMS is a kind of parallel access memory system and can simultaneously access to random pixel datas with eight types. It is possible to set a interval about pixel datas to access, too. The parallel processor built-in MAMS actually has been realized in 2003 but its performance fell short of a real time process for high-definition images. I designed a improved parallel processing system by means of addition and expansion of Memory Modules and Processing Elements of previous one. It is feasible to perform a Morphological Closing at the speed of 3 times of the previous one and 6 times of serial system.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.9
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• pp.434-441
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• 2001

The concept of network memory was introduced for the efficient exploitation of main memory in a cluster. Network memory can be used to speed up applications that frequently access large amount of disk data. In this paper, we present a memory a management algorithm that does not require prior knowledge of access patterns and that is practical to implement under the web server cluster, In addition, our scheme has a good user response time for various access distributions of web documents. Through a detailed simulation, we evaluate the performance of our memory managment algorithms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.91-94
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• 2008

The designed module save to memory after received Image from CMOS image Sensor(CIS), and set a motion of Encoder module, read from memory per one macroblock each original Image and reference image then supply or save. the time required 470 cycle when processed one macroblock. For designed construct verification, I develop reference Encoder C like JM 9.4 and I proved this module with test vector which achieved from reference encoder C.

• Journal of Korea Multimedia Society
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• v.2 no.1
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• pp.80-88
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• 1999

In this paper, we propose a Special Memory for Graphics(SMGRA) which accelerates memory access time for graphics operations. The SMGRA has a rectangular array memory architecture which has already proposed by Whelan to process pixels in the rectangle area simultaneously, but the SMGRA should improve address decoding time and reduce the number of address pins by using address multiplexing scheme. The SMGRA has a Z-value comparator in the DRAM which is to convert read-modify-write Z buffer into single-write only operation that improves approximately 50% frame buffer access bandwidth.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.156-157
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• 2007

For tens of years many advantages of Phase-Change Random Access Memory(PRAM) were introduced. Although the performance improved gradually, there are some portions which must be improved. So, we studied new constitution of $Ge_1Se_1Te_2$ chalcogenide material to improve phase transition characteristic. Actually, the performance properties have been improved surprisingly. However, crystallization time was as long as ever for amorphization time. We conducted this experiment in order to solve that problem by doping-Sb.

• Journal of Computing Science and Engineering
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• v.9 no.1
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• pp.1-8
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• 2015

Accessing and searching in a sequence of numbers are fundamental operations in computing that are encountered in a wide range of applications. One of the applications of the problem is cryptanalytic time-memory tradeoff which is aimed at a one-way function. A rainbow table, which is a common method for the time-memory tradeoff, contains elements from an input domain of a hash function that are normally sorted integers. In this paper, we present a practical indexing method for a monotonically increasing static sequence of numbers where the access and search queries can be addressed efficiently in terms of both time and space complexity. For a sequence of n numbers from a universe $U=\{0,{\ldots},m-1\}$, our data structure requires n lg(m/n) + O(n) bits with constant average running time for both access and search queries. We also give an analysis of the time and space complexities of the data structure, supported by experiments with rainbow tables.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.117-123
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• 2016

In general, PCM (Phase Change Memory) is unsuitable as a main memory because it has limitations: high read/write latency and low endurance. However, the DRAM&PCM hybrid memory with the same level is one of the effective structures for a next generation main memory because it can utilize an advantage of both DRAM and PCM. Therefore, it needs an effective page management method for exploiting each memory characteristics dynamically and adaptively. So we aim reducing an access time and write count of PCM by using an effective page replacement. According to our simulation, the proposed algorithm for the DRAM&PCM hybrid can reduce the PCM access count by around 60% and the PCM write count by 42% given the same PCM size, compared with Clock-DWF algorithm.