• The Journal of Society for e-Business Studies
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• v.8 no.3
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• pp.165-176
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• 2003

Instead of existing cell phones, PDAs are observed as leading wireless Internet devices recently Numerous applications are developed by extended usage of PDAs and it should be installed appropriately according to devices. Furthermore, when battery is discharged, all data stored in RAM(Random Access Memory) becomes obsolete. So it should be recovered or reinstalled from flash memory, backup media or something. In this paper, we present an automatic application installation system(PAIS : PDA Automatic Installation System) to solve problems that users have to install applications by themselves whenever it is necessary. With this system, users feel comfortable by saving time and effort to install each applications and application development companies save cost needed to make materials illustrating installation process. Consequently PAIS may flourish wireless Internet business.

• Proceedings of the KIEE Conference
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• 2005.07d
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• pp.3037-3039
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• 2005

The AIS(Automatic Identification System) transmits the position of ships and other information to prevent accidents which could occur in the sea. It has to be developed SOTDMA(Self-Organized Time Division Multiple Access) Algorithm which is important on wireless communication method for the AIS because It is based on ITU(International Telecommunication Union) M.1371-1 of the international standard therefore, we need to develop a performance evaluation simulator efficiently to develop and analyze SOTDMA Algorithm. this paper shows the method of designing it. Real ships access The VHF maritime mobile band but in this performance evaluation simulator several ship objects access the shared memory. Real ships are designed as the object and the wireless communication channel is designed as the shared memory. The ships apply for real virtual data which got from assistance hardware and The SOTDMA Algorithm driving state verifies the performance evaluation simulator by IEC(International Electrotechnical commission) 61993-2. After verifying results the performance evaluation simulator is correctly satisfied with IEC 61993-2. So we expect that it helps not only the AIS technology developed but also verify new SOTDMA Algorithm

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.478-480
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• 2005

The AIS(Automatic Identification System) transmits the position of ships and other information to prevent accidents which could occur in the sea. It has to be developed SOTDMA(Self-Organized Time Division Multiple Access) Algorithm which is important on wireless communication method for the AIS because It is based on ITU(International Telecommunication Union) M.1371-1 of the international standard therefore, we need to develop a performance evaluation simulator efficiently to develop and analyze SOTDMA Algorithm. This paper shows the method of designing it. Real ships access The VHF maritime mobile band but in this performance evaluation simulator several ship objects access the shared memory. Real ships are designed as the object and the wireless communication channel is designed as the shared memory. The ships apply for real virtual data which got from assistance hardware and The SOTDMA Algorithm driving state verifies the performance evaluation simulator by IEC(International Electrotechnical commission) 61993-2. After verifying results the performance evaluation simulator is correctly satisfied with IEC 61993-2. So we expect that it helps not only the AIS technology developed but also verify new SOTDMA Algorithm.

• Journal of the Korean Magnetics Society
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• v.13 no.5
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• pp.216-220
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• 2003

In this work, transmission characteristics of read and write signal were calculated when a MRAM (magnetic random access memory) cell is operated up to 10 GHz. Test device having long read and write lines was modeled in 3 dimensions to perform a simulation. The simulation was divided into two parts, read and write operations, and S-parameters were computed utilizing FEM (finite element method) algorithm. Transmission coefficients, S$\sub$21/, for read and write operations of MRAM device which was designed for a single cell test configuration were analyzed from DC to 1 GHz and DC to 10 GHz, respectively. When the insulator thickness between the bit and sense lines was increased from 500 to 1500 ${\AA}$, 3 dB attenuation frequency was increased by 3.3 times, from 135 to 430 MHz. The length of the bit and sense lines were 600 ${\mu}$m. In addition, access time was estimated by calculating the propagation delay utilizing S-parameters.

• Journal of KIISE:Databases
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• v.36 no.1
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• pp.44-49
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• 2009

In recent years, with the development of portable terminals, various searching services on large data have been provided in portable terminals. In order to search large data, most applications for information retrieval use indexes such as B-trees or R-trees. However, only a small portion of the data set is accessed by users, and the access frequencies of each data are not uniform. The existing indexes such as B-trees or R-trees do not consider the properties of the skewed access patterns. And a cache stores the frequently accessed data for fast access in memory. But the size of memory used in the cache is restricted. In this paper, we propose a new index based on disk, called J-tree, which considers user's search patterns. The proposed index is a balanced tree which guarantees uniform searching time on all data. It also supports fast searching time on the frequently accessed data. Our experiments show the effectiveness of our proposed index under various settings.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.5_6
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• pp.232-238
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• 2003

Traditional operating systems use a virtual memory to provide users with a bigger memory than a physical memory. The virtual memory augments the insufficient physical memory by the swap device. Since disks are usually used as the swap device, the cost of a page fault is relatively high compared to the access cost of the physical memory. Recently, numerous papers have investigated the Network RAM in order to exploit the idle memory in the network instead of disks. Since today's distributed systems are interconnected with high-performance networks, the network latency is far smaller than the disk access latency In this paper we design and implement the Network RAM using block device driver on Linux. This is the first implementation of the Network RAM on Linux. We propose the new reliability method to recover the page when the other workstation's memory is damaged. The system using the Network RAM as the swap device reduces the execution time by 40.3% than the system using the disk as the swap device. The performance results suggest that the new reliability method that use the processor more efficiently has the similar execution time with others, but uses smaller server memory and generates less message traffic than others.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.262-269
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• 2005

Semiconductor scientists and engineers ideally desire the faster but the cheaper non-volatile memory devices. In practice, no single device satisfies this desire because a faster device is expensive and a cheaper is slow. Therefore, in this paper, we use heterogeneous non-volatile memories and construct an efficient hierarchy for them. First, a small RAM device (e.g., MRAM, FRAM, and PRAM) is used as a write buffer of flash memory devices. Since the buffer is faster and does not have an erase operation, write can be done quickly in the buffer, making the write latency short. Also, if a write is requested to a data stored in the buffer, the write is directly processed in the buffer, reducing one write operation to flash storages. Second, we use many types of flash memories (e.g., SLC and MLC flash memories) in order to reduce the overall storage cost. Specifically, write requests are classified into two types, hot and cold, where hot data is vulnerable to be modified in the near future. Only hot data is stored in the faster SLC flash, while the cold is kept in slower MLC flash or NOR flash. The evaluation results show that the proposed hierarchy is effective at improving the access time of flash memory storages in a cost-effective manner thanks to the locality in memory accesses.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.49 no.3
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• pp.8-14
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• 2012

Improving the speed of image processing is in great demand according to spread of high quality visual media or massive image applications such as 3D TV or movies, AR(Augmented reality). SIMD computer attached to a host computer can accelerate various image processing and massive data operations. MAMS is a multi-access memory system which is, along with multiple processing elements(PEs), adequate for establishing a high performance pipelined SIMD machine. MAMS supports simultaneous access to pq data elements within a horizontal, a vertical, or a block subarray with a constant interval in an arbitrary position in an $M{\times}N$ array of data elements, where the number of memory modules(MMs), m, is a prime number greater than pq. MAMS-PP4 is the first realization of the MAMS architecture, which consists of four PEs in a single chip and five MMs. This paper presents implementation of image processing algorithms and performance analysis for MAMS-PP16 which consists of 16 PEs with 17 MMs in an extension or the prior work, MAMS-PP4. The newly designed MAMS-PP16 has a 64 bit instruction format and application specific instruction set. The author develops a simulator of the MAMS-PP16 system, which implemented algorithms can be executed on. Performance analysis has done with this simulator executing implemented algorithms of processing images. The result of performance analysis verifies consistent response of MAMS-PP16 through the pyramid operation in image processing algorithms comparing with a Pentium-based serial processor. Executing the pyramid operation in MAMS-PP16 results in consistent response of processing time while randomly response time in a serial processor.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.463-475
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• 2009

Flash memory is suitable for real time systems because of its consistent performance for random access, low power consumption and shock resistance. However, flash memory needs blocking time to perform a garbage collection to reclaim invalidated pages. Moreover, the worst-case garbage collection time is significantly longer than the best-case garbage collection time. In this paper, we propose a FTL (Flash Translation Layer) mapping scheme called KAST (K-Associative Sector Translation). In the KAST scheme, user can control the maximum association of the log block to limit the worst-case garbage collection time. Performance evaluation using simulation shows that not only KAST completes the garbage collection within the specified time but also provides about 10~15% better average performance than existing FTL schemes.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.285-285
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• 2016

Resistive random access memory devices have been widely studied due to their high performance characteristics, such as high scalability, fast switching, and low power consumption. However, fluctuation in operational parameters remains a critical weakness that leads to device failures. Although the random formation and rupture of conducting filaments (CFs) in an oxide matrix during resistive switching processes have been proposed as the origin of such fluctuations, direct observations of the formation and rupture of CFs at the device scale during resistive switching processes have been limited by the lack of real-time large-area imaging methods. Here, a novel imaging method is proposed for monitoring CF formation and rupture across the whole area of a memory cell during resistive switching. A hybrid structure consisting of a resistive random access memory and a light-emitting diode enables real-time monitoring of CF configuration during various resistive switching processes including forming, semi-forming, stable/unstable set/reset switching, and repetitive set switching over 50 cycles.