• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.451-462
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• 2009

Recently, there are many active studies to enhance low I/O performance of hard disk device. The studies on the hardware make good progress whereas those of the system software to enhance I/O performance may not support the hardware performance due to its poor progress. In this paper, we propose a new method of prefetching n-blocks into the flash memory. The proposed method consists of three steps: (1)analyzing the pattern of read requests in block units; (2)determining the number of blocks prefetched to flash memory; (3)replacing blocks according to block replacement policy. The proposed method can reduce the latency time of hard disk and optimize the power consumption of the computer system. Experimental results show that the proposed dynamic n-block method provides better average response time than that of the existing AMP(Adaptive multi stream prefetching) method by 9.05% and reduces the average power consumption than that of the existing AMP method by 11.11%.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.634-641
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• 2006

Flash memory has many advantages like non-volatility and fast I/O speed, but it has also disadvantages such as not-in-place-update data and asymmetric read/write/erase speed. For the performance of flash memory storage, it is essential for the buffer replacement algorithms to reduce the number of write operations that also affects the number of erase operations. A new buffer replacement algorithm is proposed in this paper, that delays the writes of not-cold-dirty pages in the buffer cache of flash storage. We show that this algorithm effectively decreases the number of write operations and erase operations without much degradation of hit ratio. As a result overall performance of flash I/O speed is improved.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.5
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• pp.412-421
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• 2009

Due to the physical characteristics of NAND flash memory, overwrite operations are not permitted at the same location, and therefore erase operations are required prior to rewriting. These extra operations cause performance degradation of NAND flash memory file system. Since it also has an upper limit to the number of erase operations for a specific location, frequent erases should reduce the lifetime of NAND flash memory. These problems can be resolved by delaying write operations in order to improve I/O performance: however, it will lower the cache hit ratio. This paper proposes a policy of page management using double cache for NAND flash memory file system. Double cache consists of Real cache and Ghost cache to analyze page reference patterns. This policy attempts to delay write operations in Ghost cache to maintain the hit ratio in Real cache. It can also improve write performance by reducing the search time for dirty pages, since Ghost cache consists of Dirty and Clean list. We find that the hit ratio and I/O performance of our policy are improved by 20.57% and 20.59% in average, respectively, when comparing them with the existing policies. The number of write operations is also reduced by 30.75% in average, compared with of the existing policies.

• ETRI Journal
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• v.30 no.6
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

• Journal of KIISE
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• v.44 no.10
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• pp.1005-1018
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• 2017

Recently, virtualization has become an essential component of cloud computing due to its various strengths, including maximizing server resource utilization, easy-to-maintain software, and enhanced data protection. However, since virtualization allows sharing physical resources among the VMs, the system performance can be deteriorated due to device contentions. In this paper, we first investigate the I/O overhead based on the number of VMs on the same server platform and analyze the block I/O process of the KVM hypervisor. We also propose an in-memory block cache mechanism, called QBic, to overcome I/O virtualization latency. QBic is capable of monitoring the block I/O process of the hypervisor and stores the data with a high access frequency in the cache. As a result, QBic provides a fast response for VMs and reduces the I/O contention to physical devices. Finally, we present a performance measurement of QBic to verify its effectiveness.

• Journal of KIISE:Computer Systems and Theory
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• v.36 no.6
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• pp.476-487
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• 2009

The virtual memory system in 4.4 BSD operating systems exploits a clustering scheme to reduce disk I/Os in paging out (or flushing) modified pages that are intended to be replaced in order to make free rooms in memory. Upon the page out of a victim page, the scheme stores a cluster (or group) of modified pages contiguous with the victim in the virtual address space to swap disk at a single disk write. However, it fails to find large clusters of contiguous pages if applications change pages not adjacent with each other in the virtual address space. To address the problem, we propose a new clustering scheme called Multiple-Object Clustering (MOC), which together stores multiple clusters in the virtual address space at a single disk write instead of paging out the clusters to swap space at separate disk I/Os. This multiple-cluster transfer allows the virtual memory system to significantly decrease disk writes, thus improving the page-out performance. Our experiments in the FreeBSD 6.2 show that MOC improves the execution times of realistic benchmarks such as NS2, Scimark2 SOR, and nbench LU over the traditional clustering scheme ranging from 9 to 45%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.7
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• pp.1371-1378
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• 2009

We propose a low-power eFuse one-time programmable (OTP) memory cell based on a logic process. The eFuse OTP memory cell uses separate transistors optimized at program and read mode, and reduces an operation current at read mode by reducing parasitic capacitances existing at both WL and BL. Asynchronous interface, separate I/O, BL SA circuit of digital sensing method are used for a low-power and small-area eFuse OTP memory IP. It is shown by a computer simulation that operation currents at a logic power supply voltage of VDD and at I/O interface power supply voltage of VIO are 349.5${\mu}$A and 3.3${\mu}$A, respectively. The layout size of the designed eFuse OTP memory IP with Dongbu HiTek's 0.18${\mu}$m generic process is 300 ${\times}$557${\mu}m^2$.

• The Transactions of the Korea Information Processing Society
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• v.7 no.7
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• pp.2204-2218
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• 2000

This paper proposes a dynamic storage allocation algorithm, QHF(quick-half-fit) for real-time systems. The proposed algorithm manages a free block list per each worked size for memory requests of small size, and a free block list per each power of 2 size for memory requests of large size. This algorithms uses the exact-fit policy for small sie requests and provides high memory utilization. The proposed algorithm also has the time complexity O(I) and enables us to easily estimate the worst case execution time (WCET). In order to confirm efficiency of the proposed algorithm, we compare he memory utilization of proposed algorithm with that of half-fit and binary buddy system that have also time complexity O(I). The simulation result shows that the proposed algorithm guarantees the constant WCET regardless of the system memory size and provides lower fragmentation ratio and allocation failure ratio thant other two algorithms.

• Journal of Korea Spatial Information System Society
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• v.8 no.3
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• pp.1-14
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• 2006

Recently, to efficiently support the real-time requirements of LBS and Telematics services, interest in the spatial main memory DBMS is rising. In the spatial main memory DBMS, because all spatial data can be lost when the system failure happens, the recovery system is very important for the stability of the database. Especially, disk I/O in executing the log and the checkpoint becomes the bottleneck of letting down the total system performance. Therefore, it is urgently necessary to research about the recovery system to reduce disk I/O in the spatial main memory DBMS. In this paper, we study an efficient recovery system for the spatial main memory DBMS. First, the pre-commit log method is used for the decrement of disk I/O and the improvement of transaction concurrency. In addition, we propose the fuzzy-shadow checkpoint method for the recovery system of the spatial main memory DBMS. This method can solve the problem of duplicated disk I/O on the same page of the existing fuzzy-pingpong checkpoint method for the improvement of the whole system performance. Finally, we also report the experimental results confirming the benefit of the proposed recovery system.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.8
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• pp.59-65
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• 2016

Performance optimization of applications with massive stream data processing has been performed by considering I/O data coherency problem where a memory is shared between processors and hardware accelerators. A formula for performance analyses is derived based on profiling results of system-level simulations. Our experimental results show that overall performance was improved by 1.40 times on average for various image sizes. Also, further optimization has been performed based on the parameters appeared in the derived formula. The final performance gain was 3.88 times comparing to the original design and we can find that the performance of the design with cacheable shared memory is not always.