• The Journal of the Korea Contents Association
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• v.6 no.8
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• pp.49-56
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• 2006

Urban cmmunity films have achieved the industrial modern society's idiosyncrasy Popular films have achieved the industrial growth through city as the completion of modernization. They also have represented the social meaning of urban space, and have expanded 'their political space' This filmic challenge showed diverse negative factors which were the poor's economical difficulties, the relative robbery of their education and job, and adhered class in city through developing the urban space with were hidden beyond modernity's splendor.

• Proceedings of the Korea Multimedia Society Conference
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• 1998.04a
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• pp.366-370
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• 1998

One major limitation of the efficiency of parallel computer designs has been the prohibitively high cost of parallel communication between processors and memories. Linear order concentrators can be used to build theoretically optimal interconnection schemes. Current designs call for building superconcentrators from concentrators, then using these to recursively partition the connection streams O(log2N) times to achieve point-to-point routing. Since the superconcentrators each have O(N) hardware complexity but O(log2N) depth, the resulting networks are optimal in hardware, but they are of O(log2N) depth. This pepth is not better than the O(log2N) depth Bitonic sorting networks, which can be implemented on the O(N) shuffle-exchange network with message passing. This paper introduces a new method of constructing networks using linear order concentrators and expanders, which can be used to build interconnection networks with O(log2N) depth as well as O(Nlog2N) hardware cost. (All logarithms are in base 2 throughout paper)

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2365-2374
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and pupular FPGAs(Field Programmable Gate Array) that use look-yp table memories. For improvement of technology mapping for FPGA, we use the functional decompoition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karpalgorithm extended for multiple output functions. The other is the efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental resutls show sigificant reduction in the number of CLBs and nets.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.8
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• pp.594-602
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• 1987

This paper proposes a new method of reducing the processing time and the size of consummimg memories in Hough transform. In this method, only the functional patterns are considered. The candidate points which are accumulated into the parameter space are computed in a many-to-one fashion and the parameter space is quantized dynamically to maintain a fine precision where it is needed. And a coarse-to-fine extraction method is used to reduce the processing time. The many-to-one fashional computation results in a relatively high-densed accumulation of candidate points around the parameter points corresponding to the image patterns in the image space. So, the dynamic quantization procedure can be simplified and the local maxima can be determined easily. And more effective reduction can be obtained as the dimension of parameter space is increased.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1991.10a
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• pp.29-32
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• 1991

Non-volatile SNOSFET memory devices using CMOS 1Mbit design rule(1.2$\mu\textrm{m}$), whose channel width and length are 15${\times}$1.5$\mu\textrm{m}$, 15${\times}$1.5$\mu\textrm{m}$, 2.0${\times}$15$\mu\textrm{m}$ and length are 15${\times}$1.7$\mu\textrm{m}$, respectivley, were fabricated. And the transfer, Id-Vd and switching characteristics of the devices were investigated. As a result, the 15${\times}$1.5$\mu\textrm{m}$ device was good in the transfer characteristics and the switching characteristics were favourable, which had $\Delta$V$\sub$TH/=6.3V by appling pulse voltage of V$\sub$w/=+34V, Tw=50msec.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.3
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• pp.193-198
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• 2005

NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.378-380
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• 2006

A high speed Analog parallel processing-based Viterbi decoder with a circularly connected 2D analog processing cell array is proposed. It has a 2D parallel processing structure in which an analog processing cell is placed at each node of trellis diagram is connected circulary so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error corrections, has a shorter latency and requires no path memories. In this parer, the performance of error correction as a reference position with the Analog parallel processing-based Viterbi decoder is testd via the software simulation

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.103-104
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• 2006

PRAM (Phase change Random Access Memory) is one of the most promising candidates for next generation Non-volatile Memories. The Phase change material has been researched in the field of optical data storage media. However, the characteristics required in solid state memory are quite different from optical ones. In this study, the reset current and temperature profile of PRAM cells with bottom electrode were calculated by the numerical method.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.368-369
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• 2006

Ferroelectric thin films have attracted much attention for applications in nonvolatile ferroelectric random access memories(NVFeRAM) from the view points of high speed operation, low power consumption, and large scale Integration[1,2]. Among the FRAM, BLT is of particular interest. as it is not only crystallized at relatively low processing temperature, but also shows highly fatigue resistance and large remanent polarization Meanwhile, these submicron ferroelectric capacitors were fabricated by a damascene process using Chemical mechanical polishing (CMP). BLT capacitors were practicable by a damascene process using CMP. The P-E hysteresis were measured under an applied bias of ${\pm}5V$ by using an RT66A measurement system. The electric properties such as I-V were determined by using HP4155A analysers.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.831-834
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• 1998

This paper describes a bus interface unit which is used in a 32bit high-performance multimedia RISC CPU including DSP unit. The main idea adopted in designing is that the bus interface unit enables the processor to provide on-chip functions for controlling memory and peripheral devices, including RAS-cAS multiplexing, DRAM refresh and parity generation and checking. The number of bus cycles used for a memory or I/O access is also defined by the processor, thus, no external bus controllers are required. All memories and peripheral devices can be connected directly, pin to pin, without any glue logic. That is the key point of the design.