• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1050-1052
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• 1987

This study presents mental model based on cognitive psychology and deals with implementation of associative comparator using learning automata with random access memories.

• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.54-55
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• 2000

매질의 성능이 이상적이라 가정하고, 여러 가지 시스템 파라미터로 2진 홀로그램을 저장하는 경우에 있어서, 얻을 수 있는 면적 저장밀도와 다중화 횟수를 산출하고 비교하였다. 이 논문의 결과들은 새로운 디스크형 3차원 홀로그래픽 메모리[1-3]를 연구하거나 매질을 개발함에 있어서 비교 지표로 사용될 수 있다.(중략)

• 전기의세계
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• v.24 no.5
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• pp.32-37
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• 1975

The use of a Microprocessor and PROM memories in an Electronic Loop Switching System has been described. The use provides telephone service for up to 128 subscriber lines using 32 trunks with increased reliability, maintenance capabilities, and flexibility. Date Communication between the central office terminal and the remote terminal is by FSK at 1-KHz rates over an idle trunk. Software functions and traffic handling capabilities are also described.

• The Magazine of the IEIE
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• v.25 no.7
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• pp.53-63
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• 1998

This paper reviews development trends of ferroelectric memories. Materials requirements, integration issues, device structures are reviewed for 1T-1C and 1Tr type FRAM. Other types of FRAM such as DSRAM and SFRAM are also described. Limitations in FRAM development are discussed for the viewpoint of memory concept and material properties. Finally, novel FRAM structures and operational concepts are proposed in order to avoid such limitations.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.6
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• pp.235-241
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• 2010

The static electricity generated by friction of two objects is called frictional electricity. The main cause of troubles in electronic components for military and civil use as well as in military radar appliances is found mostly in parts like LSI memories, particularly when they lose information of function momentarily while in operation, which usually leads to a fatal cause of troubles in the equipment. Troubles occur if electric noise is caused by the spark effected from discharge of static electricity from the equipment that is used nearby.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.173-178
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• 1999

The Trellis Coded Modulation(TCM) allows the considerable achievements of coding gains compare with conventional multi-level modulation without compromising bandwidth efficiency. In this paper, we are presented a design of the parallel Viterbi decoder for 16-QAM TCM decoder with large constraint length (K=9), which can be applicable for the Digital Audio Broadcasting(DAB) receiver. As a mid-term result, a parallel Branch Metric Calculator (BMC)can compute 16 BMs within 3 clocks and a parallel 16 Add-Compare-Selects (ACS) unit can compute in a single clock. And also, two 256 Path Metric Memories (PMM) 32 Trace Back(TB) memories are specially designed with shuffle exchange switches for 16 parallel accesses. As a VHDL simulation, we can find the correctness of proposed model, which can be operated 16 S per symbol. Now, we are performing the hardware reduction for realtime operation and FPGA implementation.

• Journal of the Korean Institute of Intelligent Systems
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• v.25 no.1
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• pp.97-104
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• 2015

An 'associative cube', a class of auto-associative memories, is revisited here, in which training data and hidden orthogonal basis functions such as wavelet packets or Fourier kernels, are combined in the weight cube. This weight cube has hidden units in its depth, represented by a three dimensional cubic structure. We develop an unsupervised incremental learning mechanism based upon the adaptive least squares method. Training data are mapped into orthogonal basis vectors in a least-squares sense by updating the weights which minimize an energy function. Therefore, a prescribed orthogonal kernel is incrementally assigned to an incoming data. Next, we show how a decoding procedure finds the closest one with a competitive network in the hidden layer. As noisy test data are applied to an associative cube, the nearest one among the original training data are restored in an optimal sense. The simulation results confirm robustness of associative cubes even if test data are heavily distorted by various types of noise.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.331-340
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• 2012

In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction-double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in reduced area overhead. A detailed implementation using fuse technology is also proposed in this paper.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.24.2-24.2
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• 2011

Ru is used as a bottom electrode capacitor in dynamic random access memories (DRAMs) and ferroelectric random access memories (FRAMs). The surface of the Ru needs to be planarized which is usually done by chemical mechanical polishing (CMP). Ru CMP process requires chemical slurry consisting of abrasive particles and oxidizer. A slurry containing NaIO4 and alumina particles is already proposed for Ru CMP process. However, the stability of the slurry is critical in the CMP process since if the particles in the slurry get agglomerated it would leave scratches on the surface being planarized. Thus, in the present work, the stability behavior of the slurry using a suitable anionic polyelectrolyte is investigated. The parameters such as slurry pH, polyelectrolyte concentration, adsorption time and the sequence of addition of chemicals are optimized. The results show that the slurry is stable for longer time at an optimized condition. The polishing behavior of the Ru using the optimized slurry is also investigated.