• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.86-91
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• 2022

Cache bypassing is a scheme to prevent unnecessary cache blocks from occupying the capacity of the cache for avoiding cache contamination. This method is introduced to alleviate the problems of non-volatile memories (NVMs)-based memory system. However, the prior works have been studied without considering wear-out attack. Malicious writing to a small area in NVMs leads to the failure of the system due to the limited write endurance of NVMs. This paper proposes a novel scheme to prolong the lifetime with higher resistance for the wear-out attack. First, the memory reference pattern is found by modified reuse distance calculation for each cache block. If a cache block is determined as the target of the attack, it is forwarded to higher level cache or main memory without updating the NVM-based cache. The experimental results show that the write endurance is improved by 14% on average and 36% on maximum.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.10-15
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• 2021

Cache bypassing schemes have been studied to remove unnecessary updating the data in cache blocks. Among them, a statistics-based cache bypassing method for asymmetric-access caches is one of the most efficient approach for non-voliatile memories and shows the lowest cache access latency. However, it is proposed under the condition of the normal cache system, so further study is required for the hybrid cache architecture. This paper proposes a novel cache bypassing scheme, called hybrid bypassing block selector. In the proposal, the new model is established considering the SRAM region and the non-volatile memory region separately. Based on the model, hybrid bypassing decision block is implemented. Experiments show that the hybrid bypassing decision block saves overall energy consumption by 21.5%.

• Journal of the Semiconductor & Display Technology
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• v.21 no.3
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• pp.1-6
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• 2022

Modern computer systems usually have special hardware for operations used in deep learning workload even edge computing environment. Non-volatile memories (NVMs) have been considered for alternative memory storage because they consume little static energy and occupy small area. However, there is a problem for NVMs to be directly adopted. An NVM cell has limited write endurance, so that the lifetime of NVM-based memory system is much shorter than that of conventional memory system. To overcome this problem for the deep learning system, this paper proposes a novel method to extend the lifetime based on the analysis of the deep learning workloads. If an incoming block has more than a predefined number of frequently used values, the cacheline is defined as write friendly block. During the victim selection, the cacheline has lower possibility to be chosen as victim. The experimental results show that the lifetime is increased by about 50% and energy consumption is decreased by 3% with a little performance hurt.

• Journal of the Semiconductor & Display Technology
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• v.22 no.3
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• pp.106-111
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• 2023

The importance of load-to-use latency has been highlighted as state-of-the-art computing cores adopt deep pipelines and high clock frequencies. The cascaded cache was recently proposed to reduce the access cycle of the L1 cache by utilizing differences in latencies among banks of the cache structure. However, this study assumes the cache is comprised of SRAM, making it unsuitable for direct application to non-volatile memory-based systems. This paper proposes a novel mechanism and structure for lowering dynamic energy consumption. It inserts monitoring logic to keep track of swap operations and write counts. If the ratio of swap operations to total write counts surpasses a set threshold, the cache controller skips the swap of cache blocks, which leads to reducing write operations. To validate this approach, experiments are conducted on the non-volatile memory-based cascaded cache. The results show a reduction in write operations by an average of 16.7% with a negligible increase in latencies.

• Journal of the Korean Institute of Educational Facilities
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• v.27 no.2
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• pp.28-32
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• 2020

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.55-62
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• 2012

The development of memory design and process technology enabled the production of high density memory. As the weight of embedded memory within aggregate Systems-On-Chips(SoC) gradually increases to 80-90% of the number of total transistors, the importance of testing embedded dual-port memories in SoC increases. This paper proposes a new micro-code based programmable memory Built-In Self-Test(PMBIST) architecture for dual-port memories that support test various test algorithms. In addition, various test algorithms including March based algorithms and dual-port memory test algorithms are efficiently programmed through the proposed algorithm instruction set. This PMBIST has an optimized hardware overhead, since test algorithm can be implemented with the minimum bits by the optimized algorithm instructions.

• Journal of Internet Computing and Services
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• v.11 no.6
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• pp.41-50
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• 2010

As time goes by, most of information escapes human being's memory even though he/she tries hard to remember the information. On the other hand, when a human being takes a look at an image, he/she recollects once forgotten past memories and relates a specific object in the photo with associated words, which trigger new memories. Beside, he/she feels the affection of that time by the recalled memory. Therefore, this paper proposes an augmented memory system that assists recollection of user's past memories by using the images in social network services and user's dictionary for associated words. In the proposed system, if a user selects an object in an image, words associated with the object is provided to the user. If the user selects one of the associated words, the proposed system offers the list of other images containing the object of the selected word. The repetition of the aforementioned process can make the user recollect his/her memory and stimulate his/her affection. It is expected that the proposed system will be useful for revitalizing social network services.

• Journal of KIISE:Software and Applications
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• v.29 no.11
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• pp.826-836
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• 2002

We need an enormous amount of memories for name spaces as well as additional processors if we are to effectively exploit a massively parallelism in nested loops of functional languages such as Id. If there is no sufficient amount of memories enough to exploit that parallelism, the execution of programs can be aborted during the unfolding of loops. Additionally, if loops are overunfolded, compared with the number of processors available, the system performance can be degraded severely due to the overhead of loop unfolding. This paper suggests and analyzes an algorithm which can be used to effectively unfold nested loops of functional languages on multithreaded architectures. This algorithm has a feature to unfold a given nested loop safely and near optimally, considering the system resources of processors and memories available when the loop is to be unfolded.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.30-36
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• 2010

In recent memories, repair is an unavoidable method to maintain its yield and quality. Although many word oriented memories as well as embedded memories in system-on-chip (SOC) consists of multiple local memory blocks with a global spare architecture, most of previous studies on built-in redundancy analysis (BIRA) algorithms have focused on single memory block with a local spare architecture. In this paper, a new BIRA algorithm for multiple blocks with a global spare architecture is proposed. The proposed BIRA is basd on CRESTA which is able to achieve optimal repair rate with almost zero analysis time. In the proposed BIRA, all repair solutions for local memory blocks are analyzed by local analyzers which belong to each local memory block and then compared sequentially and judged whether each solution can meet the limitation of the global spare architecture or not. Experimental results show that the proposed BIRA achieves much faster analysis speed compared to previous BIRAs with an optimal repair rate.

• Korean Journal of Biological Psychiatry
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• v.19 no.1
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• pp.1-8
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• 2012

The mechanism of psychotherapy is explained by the recent developments in neuroscience and neuroimaging. The purpose of this study is to understand the nature of psychotherapy and to discuss the future of psychotherapy improvement with the help of advances of the neurobiological findings in psychotherapy. For this study, we investigated a wide range of materials. We searched for various researches on psychotherapy, brain, and neurobiology. In addition to the conventional psychodynamic psychotherapy, we investigated research findings on cognitive behavioral therapy, interpersonal psychotherapy and eye movement desensitization and reprocessing (EMDR). Moreover, based on the actual experiences of treating patients, we speculated the neurobiological mechanisms of the process and results of psychotherapy. With the development of neuroscience, we are now able to understand the personal consciousness, unconsciousness and developmental process. Also subdividing the disease is made possible. Personalized treatment has become available, and we are able to predict the prognosis of patients. Our memories are composed by implicit memory and explicit memory. By psychotherapy, we can consciously remember explicit memory, and it becomes easier to explore implicit memory through free association. Through psychotherapy, we will also be able to learn the effect of acquired environment and experience. Psychotherapy is able to correct human behaviors by modifying the memories. Through the regulation of emotions, it becomes possible to modify the memories and correct the behaviors. In this process, doctor-patient relationship is the main factor which cause positive treatment effects. Furthermore imagination therapy or unconscious, non-verbal stimuli could bring about positive treatment effects. Now psychotherapy could be explained and studied by neuroscientific researches. In this sense, we could provide the direction of future advances in neuroscience by the neurobiological understanding of psychotherapy.