• ETRI Journal
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• v.27 no.5
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• pp.569-578
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• 2005

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on-chip 1 to 6 GHz up-conversion and 1 to 8 GHz down-conversion mixers using a 0.8 mm SiGe hetero-junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up-conversion mixer was implemented on-chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up-conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down-conversion mixer was implemented on-chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down-conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.1
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• pp.98-103
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• 1989

A new system for logic optimization at gate-level is proposed in this paper. Ths system is rule-based, i which the rules represent the local trnsformation replacing a portion of circuits with the simplified equivalent circuits. In this system, 'rule generalization' and 'local optimization' are proposed for effective pattern matching. Rule generalization is used to reduce the circuit-search for pattern matching, and local optimization, to exclude unnecessary circuit-search. In additionk, in order to reduce unnecessary trial of pattern matching, the matching order of circuit patern is included in the rule descriptions. The effectiveness of this system is shown by its application ot the circuits which are generated by a hardware compiler.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.3
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• pp.283-291
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• 2015

In this paper, a negative impedance converter, the key element of non-Foster matching to enhance the bandwidth of matching high Q-factor passive element, is presented. Proposed negative impedance converter is implemented by the topology of Linvill's transistor negative impedance converter circuit. It is hard to forecast the operation of negative impedance circuit, because it is composed of gain element and positive feedback. Therefore the negative impedance circuit is implemented by hybrid type beforehand to check out the feasibility and it is designed by integrated circuit. The integrated circuit is fabricated by commercial $0.18{\mu}m$ SiGe BiCMOS process, and non-Foster matching is observed at 700~960 MHz band by cancelling the target reactance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1B
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• pp.47-55
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• 2009

In recent network intrusion detection systems, regular expressions are used to represent malicious packets. In order to process incoming packets through high speed networks in real time, we should perform hardware-based pattern matching using the configurable device such as FPGAs. However, operating speed of FPGAs is slower than giga-bit speed network and so, multi-byte processing per clock cycle may be needed. In this paper, we propose a hardware architecture of multi-byte based regular expression pattern matching and implement the pattern matching circuit generator. The throughput improvements in four-byte based pattern matching circuit synthesized in FPGA for several Snort rules are $2.62{\sim}3.4$ times.

• ETRI Journal
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• v.34 no.3
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• pp.454-457
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• 2012

A miniaturized planar digital video broadcasting terrestrial (DVB-T) antenna, which is composed of a patterned helical line, an open stub, and an impedance matching circuit on an FR4 (${\varepsilon}_r$=4.4) substrate for portable media player applications, is presented in this letter. The antenna has monopole-like, omni-directional radiation characteristics and a wide impedance bandwidth (VSWR<3) in the DVB-T band from 174 MHz to 230 MHz at the VHF band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.3
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• pp.286-291
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• 2013

In this paper, a compact rectenna system is designed using a circular sector antenna with harmonic-rejecting characteristics and a direct impedance matching method. The system is designed with bandpass filtering performed by the harmonic-rejection of the circular sector antenna and without impedance matching circuit for the diodes by the direct impedance matching technique. Therefore, while the rectifying circuit of the proposed system can be implemented without a bandpass filter and a impedance matching circuit, it is integrated on the back side of the antenna using precise fabrication techniques for coaxial feedings without degrading the system performances corresponding to the feeding points. From the experimental results, the optimized rectenna system has presented excellent performances of a conversion efficiency of more than 52 % and a conversion voltages of more than 1.5 V at 2.5 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.11
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• pp.1098-1103
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• 2013

A low-noise amplifier(LNA) using series RLC matching network and resistive feedback at 8 GHz is presented. Inductive degeneration is used for the input matching with which the proposed LNA shows quite a wide bandwidth in terms of $S_{21}$. An equivalent circuit model is deduced for input matching by conversion from parallel circuit to series resonant circuit. By exploiting the resistive feedback and series RLC input matching, fully integrated LNA achieves maximum $S_{21}$ of 8.5 dB(peak to -3 dB bandwidth is about 3.5 GHz) noise figure of 5.9 dB, and IIP3 of 1.6 dBm while consuming 7 mA from 1.2 V supply.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.2045-2049
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• 2018

An antenna arrays for a satellite navigation systems require more antenna elements to mitigate multiple jamming signals. In order to maintain the small array size while increasing the number of antenna elements, miniaturization technique is essential for antenna design. In this work, an electrically small circular microstrip patch antenna with a 3 dB hybrid coupler is designed as an element antenna, where the 3 dB hybrid coupler can yield the circularly polarized radiation characteristic. The miniaturized element antenna typically has too large capacitance in GPS L1 and GLONASS G1 bands, making it difficult to match with a single stand-alone non-Foster matching circuit (NFMC) in a stable state. Therefore, we propose a new matching technique, referred to as the hybrid matching method, which consists of a NFMC and a passive circuit. This passive tuning circuit manages reactance of antenna elements at an appropriate capacitance without a pole in the operating frequency range. The antenna array is fabricated, and the measured results show a reflection coefficient of less than -10 dB and an isolation of greater than 50 dB. In addition, peak gain of the proposed antenna is increased by 22.3 dB compared to the antenna without the hybrid matching network.

• The Transactions of the Korean Institute of Power Electronics
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• v.24 no.3
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• pp.161-168
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• 2019

This study introduces a new topology to decrease the voltage stress experienced by a 13.56 MHz electrical variable capacitor (EVC) circuit with an asymmetrical switch structure applied to the impedance matching circuit of a radio frequency (RF) plasma system. The method adopts a symmetrical switch structure instead of an asymmetrical one in each of the capacitor's leg in the EVC circuit. The proposed topology successfully reduces voltage stress in the EVC circuit due to the symmetrical charging and discharging mode. This topology can also be applied to the impedance matching circuit of a high-power and high-frequency RF etching system. The target features of the proposed circuit topology are investigated via simulation and experiment. Voltage stress on the switch of the EVC circuit is successfully reduced by more than 40%.

• Journal of the Korea Computer Industry Society
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• v.5 no.1
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• pp.177-182
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• 2004

In sonar sensor design impedance matching design to each sensor affects the whole weighting circuit characteristic very much. But there are many examples that it is made by hands or very simple modeling designs. So these design works make trial and error because it is the limitation of flexible correspondence to the many sensors and follows many errors. This study explains organizations and skills in the sensor modeling package design program with real sonar sensor characteristic measure as the first step in impedance matching design.