• Journal of the Microelectronics and Packaging Society
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• v.7 no.2
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• pp.1-6
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• 2000

X-ray lithography mask with SiC membrane and Ta absorber patterns has been fabricated using ECR plasma CVD, d.c. magnetron sputtering, and ECR plasma etching. The stress of stoichiometric SiC film was adjusted by rapid thermal annealing under $N_2$, ambient. Adjusting the working pressure during sputtering process resulted in a near-zero residual stress, reasonable density, and smooth surface morphology of Ta film. Cl-based plasma showed a good etching characteristics of Ta, and two-step etching process was implemented to suppress microloading effect fur sub-quarter $\mu\textrm{m}$ patterning.

• Journal of IKEEE
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• v.17 no.3
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• pp.221-228
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• 2013

About functional parameters of a LED/UVLED (Light Emitting Diode/Ultra Violet LED), one of the most important parameters is the I-V characteristic. By researching factors affect to the I-V characteristic of uvled, we found that beside of the structure of the device itself, there is the influence of the electrode materials, electrode shapes, the process of wiring and packaging. In this work, we want to improve the performance of UVLED to find out the optimal mask design principles. The study is based on theoretical mathematical models, as well as the use of simulation software tool Comsol. From all results obtained, the team has improved mask design to manufacture electrodes for GaN-based UVLED. Electrode masks are designed by three softwares, which are Intellisuite, Klayout and AutoCad. Intellisuite masks would be used in fabrication simulation while Klayout and AutoCad are used to fabricate electrodes in experiments. As well as, we silmulated the structure of an uvled 355nm emission wavelength by TCAD software, in order to compare with uvled sample that has the same emission wavelength.

• Journal of the Semiconductor & Display Technology
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• v.20 no.2
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• pp.126-130
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• 2021

The ball grid array is one of the packaging methods that used in high density printed circuit board. Solder void defects caused by voids in the solder ball during the BGA process do not directly affect the reliability of the product, but it may accelerate the aging of the device on the PCB layer or interface surface depending on its size or location. Void inspection is important because it is related in yields with products. The most important process in the optical inspection of solder void is the segmentation process of solder and void. However, there are several segmentation algorithms for the vision inspection, it is impossible to inspect all of images ideally. When X-Ray images with poor contrast and high level of noise become difficult to perform image processing for vision inspection in terms of software programming. This paper suggests the solution to deal with the suggested problem by means of using Mask R-CNN instead of digital image processing algorithm. Mask R-CNN model can be trained with images pre-processed to increase contrast or alleviate noises. With this process, it provides more efficient system about complex object segmentation than conventional system.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.2
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• pp.41-47
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• 2010

The effect of PCB and BGA pad designs was investigated on the mechanical property of Pb-free solder joints. The mechanical property of solder joint was tested by three different test methods of drop impact tests, bending impact test, and high speed shear test. Two kinds of pad design such as NSMD (Non-Solder Mask Defined) and SMD (Solder Mask Defined) were applied with the OSP finished Pb-free solder (Sn-3.0Ag-0.5Cu, Sn-1.2Ag-0.5Cu). in the drop impact test and bending impact test, the characterized lifetime showed the same tendency, and SMD design showed better mechanical property of solder joint than NSMD regardless of test method, which was due to the different crack path. The fracture crack on SMD pad was propagated along the intermetallic compound (IMC) layer of solder joint, while the fracture crack on NSMD pad propagated through upper edge of land which shields pattern. In the high speed shear test, pad lift occurred on the solder joint of NSMD. SMD/SMD combination of pad design consequently illustrated the best mechanical property of BGA/PCB solder joint, followed by SMD/NSMD, NSMD/SMD, and NSMD/NSMD.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.275-280
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• 2005

We propose a new approach to greatly simplify the fabrication of conventional nanoimprint lithography (NIL) by combined nanoimprint and photolithography (CNP). We introduce a hybrid mask mold (HMM) made from UV transparent material with a UV-blocking Cr metal layer placed on top of the mold protrusions. We used a negative tone photo resist (PR) with higher selectivity to substrate the CNP process instead of the UV curable monomer and thermal plastic polymer that has been commonly used in NIL. Self-assembled monolayer (SAM) on HMM plays a reliable role for pattern transfer when the HMM is separated from the transfer layer. Hydrophilic $SiO_2$ thin film was deposited on all parts of the HMM, which improved the formation of SAM. This $SiO_2$ film made a sub-10nm formation without any pattern damage. In the CNP technique with HMM, the 'residual layer' of the PR was chemically removed by the conventional developing process. Thus, it was possible to simplify the process by eliminating the dry etching process, which was essential in the conventional NIL method.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.39-43
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• 2001

$SiC_{x}N$_{y}$ film is deposited by electron cyclotron resonance plasma chemical vapor deposition system using $SiH_4$(5% in Ar), $CH_4$ and $N_2$. Ternary phase $SiC_{x}N$_{y}$ thin film deposited at the microwave power of 600 W and substrate temperature of 700 contains considerable amount of strong C-N bonds. Change in $CH_4$flow rate can effectively control the residual film stress, and typical surface roughness of 34.6 (rms) was obtained. Extreme]y high hardness (3952 Hv) and optical transmittance (95% at 633 nm) was achieved, which is suitable for a LIGA mask membrane application.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1272-1273
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• 2009

We demonstrate conformal phosphor coating and patterning methods on light emitting diodes (LEDs) using image processing based optofluidic maskless lithography (IP-OFML) system in microfluidic channels. IP-OFML allows a real-time detection and dynamic mask generation for packaging of randomly dispersed microchips. Our system detects each chip by considering rotation of the chip through image processing regardless of their arrangement error. Therefore, it precisely packages the chip making conformal polymer layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.65-68
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• 2013

A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process. A selective solder bumping mechanism without the mask is based on the material design of SBM. Maskless screen printing process can implement easily a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology. Its another advantage is ternary or quaternary lead-free SoP can be formed easily. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 ${\mu}m$ is, successfully, formed.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.181-186
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• 2005

We fabricated thin films of polystyrene-block-poly(methyl methacrylate)(PS -b-PMMA) on the self-assembled monolayers(SAM) of 3-(p-methoxyphenyl)propyltrichlorosilane(MPTS) on silicon wafers. Cylindrical nanodomains of PMMA or PS were oriented perpendicular to the surface of silicon wafers due to the neutral affinity of the SAM to PS and PMMA blocks. By selective removal of the PMMA block with UV irradiation and washing, nanoporous films and nanorod assemblies were produced. The nanoporous film can be used for a nanolithographical mask.