• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.5 no.2
• /
• pp.408-427
• /
• 2011

Intensive computational complexity is an obstacle of enabling multiview video coding for real-time applications. In this paper, we present a fast macroblock (MB) mode selection algorithm for B frames which are based on the computational complexity analyses between the MB mode selection and reference frame selection. Three strategies are proposed to reduce the coding complexity jointly. First, the temporal correlation of MB modes between current MB and its temporal corresponding MBs is utilized to reduce computational complexity in determining the optimal MB mode. Secondly, Lagrangian cost of SKIP mode is compared with that of Inter $16{\times}16$ modes to early terminate the mode selection process. Thirdly, reference frame correlation among different Inter modes is exploited to reduce the number of reference frames. Experimental results show that the proposed algorithm can promote the encoding speed by 3.71~7.22 times with 0.08dB PSNR degradation and 2.03% bitrate increase on average compared with the joint multiview video model.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.44 no.4 s.316
• /
• pp.8-16
• /
• 2007

For the improvement of coding efficiency, the H.264/AVC video coding standard employs new coding tools compared with existing coding standards. However, due to these new coding tools, the complexity of K264/AVC standard encoder is greatly increased. Specifically, the inter/intra mode decision method using RDO(rate-distortion optimization) technique is one of the most complex parts in H.264/AVC. In this paper, we focus on the complexity reduction in macroblock mode decision. In the proposed method, we reduce the complexity of the $4{\times}4$ mode decision process using $4{\times}4$ simple square filters, and using spatial block correlation method. Additionally, exploiting the best mode of sub_macroblock in $Inter8{\times}8$ mode, we proposed an algorithm to eliminate some intra modes in current macroblock mode decision process. In addition, we employed a method to raise the probability to select SKIP, $Intra16{\times}16$, and $Intra16{\times}16$ modes which usually show low complexity and low bitrate compared with other modes. From the simulation results, the proposed algorithm reduce the encoding time by maximum 83% of total, and reduce the bitrate of the overall sequences by $8{\sim}10%$ on the average compared with existing coding methods.

• Proceedings of the IEEK Conference
• /
• 2003.07d
• /
• pp.1527-1530
• /
• 2003

Video is an important and challenge media and requires sophisticated indexing schemes for efficient retrieval from visual databases. Scene change detection is the first step for automatic indexing of video data. Recently, several scene change detection algorithms in the pixel and compressed domains have been reported in the literature. However, using pixel methods are computationally complex and are not very robust in detecting scene change detection. In this paper, we propose robust abrupt scene change detection using macroblock type and DC coefficient. Experimental results show that the proposed algorithm is robust for detection of most abrupt scene changes in the compressed domain.

• Proceedings of the KIEE Conference
• /
• 2005.05a
• /
• pp.167-169
• /
• 2005

The occurrence of a single bit error in transmission bitstream leads to serious temporal and spatial errors. Because moving picture coding as MPEG-2 based on block coding algorithm uses variable length coding and motion compensation coding algorithm. In this paper, we propose algorithm to conceal occurred error of I-frames in transmission channel using data of the neighboring blocks in decoder. We divide a damaged macroblock of I-frame into four sub blocks and compose new macroblock using the neighboring blocks for each sub block. We estimate the block with minimum difference value through block matching with previous frame for new macroblocks and replace each estimated block with damaged sub block in the same position. Through simulation results, the proposed algorithm will be applied to a characteristic of moving with effect and shows better performance than conventional error concealment algorithms from visual and PSNR of view.

• International Journal of Internet, Broadcasting and Communication
• /
• v.7 no.2
• /
• pp.168-172
• /
• 2015

In this paper, a balanced bitrate control in transcoding process based on video complexity measure for multi-view system which simultaneously shows multiple channels or video contents in single screen, is proposed. In order to consider the total quality of multiple video streams, the proposed algorithm reduces the complexity of multiple video stream and video quality differences at the same time by controlling bitrates of each stream by weighting when they are stitched for single screen. For the measure of complexity and quality differences between video streams, two different data: histogram of macroblock type and bitrate for each stream are used. The experimental result indicates that proposed algorithm decreases fluctuation of quality difference between videos in the multi-view system.

• Proceedings of the KIEE Conference
• /
• 2005.10b
• /
• pp.529-531
• /
• 2005

A block-based fast motion estimation algorithm is proposed in this paper to perform motion estimation based on the efficiently reduced search ranges in MPEG-4(ERS). This algorithm divides the search areas into several small search areas and the candidate small search area that has the lowest average of sum norm difference between current macroblock and candidate macroblock is chosen to perform block motion estimation using the Nobel Successive Elimination Algorithm (NSEA). Experimental results of the proposed algorithm show that the averaging PSNR improvement is better maximum 0.125 dB than other tested algorithms and bit saving effect is maximum 20kbps for some tested sequences in low-bit rate circumstance.

• Proceedings of the IEEK Conference
• /
• 2003.11a
• /
• pp.125-128
• /
• 2003

In this paper, we propose two methods for complexity reduction of intra prediction in H.264/AVC. One is skipping of intra prediction using inter prediction cost at current macroblock in current P picture, average of intra prediction cost in previous I picture, and average of inter prediction cost in previous P picture. The other is skipping of intra 16$\times$16 prediction using intra 4$\times$4 prediction cost and modes. As a result, complexity of intra prediction in P picture and that of intra 16$\times$16 prediction in intra prediction macroblock can be reduced by about 80~99％ and 50~93％, respectively.

• Proceedings of the IEEK Conference
• /
• 1999.06a
• /
• pp.601-604
• /
• 1999

We propose a new hierarchical motion estimator architecture that supports the advanced prediction mode of recent low bit-rate video coders such as H.263 and MPEG-4. In the proposed VLSI architecture, a basic searching unit (BSU) is commonly utilized for all hierarchical levels to make a systematic and small sized motion estimator. Since the memory bank of the proposed architecture provides scheduled data flow for calculating 8$\times$8 block-based sum of absolute difference (SAD), both a macroblock-based motion vector (MV) and four block-based MVs are simultaneously obtained for each macroblock in the advanced prediction mode. The proposed motion estimator gives similar coding performance compared with full search block matching algorithm (FSBMA) while achieving small size and satisfying the advanced prediction mode.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.6 no.4
• /
• pp.227-233
• /
• 2006

In order to reduce blocking artifacts and improve compression efficiency, H.264/AVC standard employs an adaptive in-loop deblocking filter. This paper proposes a new hardware architecture of the deblocking filter that employs a four-stage pipelined structure with an efficient data distribution. The proposed architecture allows a simultaneous supply of eight data samples to fully utilize the pipelined filter in both horizontal and vertical filterings. This paper also presents a new filtering order and data reuse scheme between consecutive macroblock filterings to reduce the communication for external memory access. The number of required cycles for filtering one macroblock (MB) is 357 cycles when the proposed filter uses dual port SRAMs. This execution speed is only 41.3% of that of the fastest previous work.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.91-94
• /
• 2008

The designed module save to memory after received Image from CMOS image Sensor(CIS), and set a motion of Encoder module, read from memory per one macroblock each original Image and reference image then supply or save. the time required 470 cycle when processed one macroblock. For designed construct verification, I develop reference Encoder C like JM 9.4 and I proved this module with test vector which achieved from reference encoder C.