• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.5C
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• pp.683-691
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• 2004

To transmit MPEG-2 video on an errorneous channel, a number of error control techniques are needed. Especially, error concealment techniques which can be implemented on receivers independent of transmitters are essential to obtain good video quality. In this paper, prediction of motion vector and an adaptive boundary matching algorithm are presented for temporal error concealment. Before the complex BMA, we perform error concealment by a motion vector prediction using neighboring motion vectors. If the candidate of error concealment is not satisfied, search range and reliable boundary pixels are selected by the temporal activity or motion vectors and a damaged macroblock is concealed by applying an adaptive BMA. This error concealment technique reduces the complexity and maintains a PSNR gain of 0.3∼0.7㏈ compared to conventional BMA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.1-9
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• 2010

In this paper, the novel architecture of Intra-prediction & DCTQ hardware, which can process for the Full HD image($1980{\times}1088$@30fps) in realtime, is proposed. The cycle optimization method for the overall cycle of prediction, transform, scaling, descaling, and reconstruction is proposed. To reduce the cycle in the $4{\times}4$ prediction, the quantization process is performed during the prediction cycle and pre-selection of 2 modes among the 9 modes is performed to reduce the hardware area. To reduce the hardware of $16{\times}16$ and $8{\times}8$ prediction, the sharing logic between 2 prediction is utilized. The proposed architecture can process the 30frame/sec of full HD image in 108 MHz clock and operate 425 cycle for one macroblock.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.21-29
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• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.5
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• pp.165-174
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• 2010

The H.264/AVC standard obtained better performance than previous compression standards, but it also increased the computational complexity of CODEC simultaneously. Various techniques recently included at the KTA software developed by VCEG also were increasing its complexity. Especially adaptive interpolation filter has more complexity than two times due to development for coding efficiency. In this paper, we propose low-complexity filter bank to improve speed up of decoding and coding gain. We consists of filter bank of a fixed-simple filter for low-complexity and adaptive interpolation filter for high coding efficiency. Then we compensated using optimal filter at each macroblock-level or frame-level. Experimental results shows a similar coding efficiency compared to existing adaptive interpolation filter and decoding speed of approximately 12% of the entire decoder gained.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.108-123
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• 2007

As H.264/AVC standard has proven to be a key technology of multimedia application, many researches to improve H.264/AVC standard are actively conducted. Those researches are conducted in various ways such as algorithm analysis and improvement or structure enhancement for reducing bottlenecks of performance. Even though targets and directions of those studies are not the same, performance of H.264/AVC standard is commonly analyzed in the early phase. In analysis phase, potential problems with H.264/AVC standard are identified and the most critical problem which has serious effects on performance is determined. Therefore, analysis phase is one of the important steps to decide overall directions and targets of the research. This research proposes a mathematical model which can be used in the early performance analysis phase to estimate performance in conducting research of improving the performance of H.264/AVC Baseline Profile decoder. The proposed model is designed by considering many variables of H.264/AVC decoder operation so that it is easy to predict its performance according to changes in each element.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.7
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• pp.52-60
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• 2008

The deblocking filter in the H.264/AVC video coding standard helps to reduce the blocking artifacts produced in the decoding process. But it consumes one third of the computational complexity in H.624/AVC decoder, which advocates an efficient design of a hardware accelerator for filtering. This paper proposes an architecture of deblocking filter using two filters and some registers for data reuse. Our architecture improves the throughput and minimize the number of external memory access by increasing data reuse. After initialization, two filters are able to perform filtering operation simultaneously. It takes only 96 clocks to complete filtering for one macroblock. We design and synthesis our architecture using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 200MHz.

• Journal of IKEEE
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• v.17 no.4
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• pp.418-427
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• 2013

In this paper, we propose a parallel deblocking filter algorithm for H.264/AVC video standard. The deblocking filter has different filter processes according to boundary strength (BS) and each filter process requires various conditional calculations. The order of filtering makes it difficult to parallelize deblocking filter calculations. The proposed deblocking filter algorithm is performed on PRAGRAM which is a 1-D coarse grained reconfigurable architecture (CGRA). Each filter calculation is accelerated using uni-directional pipelined architecture of PRAGRAM. The filter selection and the conditional calculations are efficiently performed using dynamic reconfiguration and conditional reconfiguration. The parallel deblocking filter algorithm uses 225 cycles to process a macroblock and it can process a full HD image at 150 MHz.

• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.793-796
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• 2011

H.264/AVC compresses video data by applying DCT transform, quantization and entropy coding processes to the residual signal obtained by inter/intra prediction. This paper proposes a method enhancing an existing DC offset adjustment technology which uses information of neighboring blocks to reduce residual information for improving coding efficiency. DC offset information is not sent over bitstreams, but calculated in the same way both in the decoder and in the encoder. Experimental results show that the proposed method enhances coding efficiency by 0.25% in average BD-Rate compared to H.264/AVC and gives better or worse coding efficiency compared to the existing DC offset method depending on video sequences with coding efficiency degradation by 0.09% in average BD-Rate. This experimental results also show that further coding efficiency improvement is possible by applying the proposed method adaptively to slice or macroblock coding units.

• Journal of Broadcast Engineering
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• v.12 no.5
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• pp.491-502
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• 2007

In this parer, we propose an efficient intra prediction mode decision scheme in Scalable Video Coding(SVC) which is an emerging video coding standard as an extension of H.264/MPEG-4 AVC(Advanced Video Coding). The proposed method in base on the characteristic of macroblock smoothness follows the statistical analysis of intra prediction mode in an enhancement layer and it decides a candidate intra prediction mode. We also propose an early termination scheme for Intra_BL mode decision where the RD cost value of Intra_BL is utilized. Simulation results show that the proposed method reduces 54.67% of the computation complexity of intra prediction coding, while the degradation in video quality is negligible; for low QP values, the average PSNR loss is very negligible, equivalently the bit rate increases by 0.011%. For high QP values, the average PSNR loss is less than 0.01dB, which equals to 0.249% increase in bitrate.

• Journal of IKEEE
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• v.17 no.3
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• pp.352-359
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• 2013

This paper proposes an entropy coding unit for H.264/AVC baseline profile. Entropy coding requires code tables for macroblock encoding. There are patterns in codewords of each code tables. In this paper, the patterns between codewords are analyzed to reduce the hardware cost. The entropy coding unit consists of Exp-Golomb unit and CAVLC unit. The Exp-Golomb unit can process five code types in a single unit. It can perform Exp-Golomb processing using only two adders. While typical CAVLC units use various code tables which require large amounts of resources, the sizes of the tables are reduced to about 40% or less of typical CAVLC units using relationships between table elements in the proposed CAVLC unit. After the Exp-Golomb unit and the CAVLC unit generate code values, the entropy unit uses a small size shifter for bit-stream generation while typical methods are barrel shifters.