• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.301-309
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• 2002

In this paper, we propose the effective implementation of various nonlinear combiners using by PS-LFSR: m-parallel memoryless-nonlinear combiner, m-parallel memory-nonlinear combiner, m-parallel nonlinear filter function, and m-parallel clock-controlled function. Finally, we propose m-parallel LILI-128 stream cipher as an example of the parallel implementation, and we determine its cryptographic security and performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.4
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• pp.859-867
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• 2010

In this paper, we propose some parallel structures of the word-based nonlinear combining functions in word-based stream cipher, high-speed versions of general (bit-based) nonlinear combining functions. Especially, we propose the high-speed structures of popular four kinds in word-based nonlinear combiners using by PS-WFSR (Parallel-Shifting or Parallel-Structured Word-based FSR): m-parallel word-based nonlinear combiner without memory, m-parallel word-based nonlinear combiner with memories, m-parallel word-based nonlinear filter function, and m-parallel word-based clock-controlled function. In addition, we propose an implementation example of the m-parallel word-based DRAGON stream cipher, and determine its cryptographic security and performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.5B
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• pp.554-560
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• 2001

통신망의 급격한 발전과 통신 속도의 향상에 따라 암호 알고리듬의 고속화 필요성이 절실하다. 본 논문에서는 LFSR을 고속화하기 위하여 한 클럭에 m번의 이동이 이루어지는 고속 병렬형 PS-LFSR을 제안하였고, 이를 기본으로 다수의 키 수열 발생기를 병렬 연결하여 속도를 개선시킨 병렬형 스트림 암호를 제안하였다. 그리고 병렬형 스트림 암호 예로서 m-병렬 합산 수열 발생기(m-parallel SUM-BSG)를 제안하여 m=8인 병렬 발생기를 세부 설계 예시하였으며, 제안된 발생기는 기존의 비도 수준을 유지하면서 처리 속도를 m배 높을 수 있음을 확인하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2000.10a
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• pp.805-808
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• 2000

통신망의 급격한 발전과 통신 속도의 향상에 따라 암호 알고리듬의 고속화 필요성이 절실하다. 본 논문에서는 LFSR을 고속화하기 위하여 한 클럭에 m번의 이동이 이루어지는 고속형 HS-LFSR을 제안하였고, 이를 기본으로 다수의 키 수열 발생기를 병렬 연결하여 속도를 개선시킨 병렬형 스트림암호를 제안하였다. 그리고 병렬형 스트림 암호 예로서 m-병렬 합산 수열 발생기(m-parallel SUM-BSG)를 제안하여 m = 8인 병렬 발생기를 세부 설계 예시하였으며, 제안된 발생기는 기존의 비도 수준을 유지하면서 처리 속도를 m배 높일 수 있음을 확인하였다.

• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.62-65
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• 2014

근사문자열매칭 알고리즘은 검색엔진, 컴퓨터보안, 생물정보학 등 많은 분야에서 연구되고 있다. 근사문자열매칭에서는 거리함수를 이용하여 오차를 측정한다. 거리함수로는 해밍거리, 편집거리, 확장편집거리 등이 있다. 이때 확장편집거리는 mn) 시간과 공간에 계산할 수 있으며, 최근 m개의 쓰레드를 이용하여 O(m+n) 시간과 O(mn) 공간을 이용한 병렬알고리즘이 제시되었다. 본 논문에서는 기존의 확장편집거리를 계산하는 병렬알고리즘을 개선한 효율적인 병렬알고리즘을 제시한다. 기존의 병렬알고리즘을 최적화하고, 기존의 병렬알고리즘, 전역메모리만 사용한 최적화된 병렬알고리즘, 공유메모리를 활용한 최적화된 병렬알고리즘의 수행시간을 비교한다. 실험 결과, 개선된 병렬알고리즘이 기존의 병렬알고리즘보다 전처리단계에서 16 ~ 63배 이상, 모든 단계에 대해 19 ~ 24배 이상 빠른 수행시간을 보였다.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1636-1651
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• 1997

In task parallel language like Fortran M, programmer writes a task parallel program using parallel constructs which is provided. When some data dependencies exist between called procedures in various applications, it is difficult for programmer to write program according to their dependencies. Therefore, it is desirous that compiler can detect some implicit parallelisms and transform a program to parallelized form by using the task parallel constructs like PROCESSES block or PROCESSDO loop of Fortran M. But current task parallel language compilers can't provide these works. In this paper, we analyze the cases according to dependence relations and detect the implicit parallelism which can be transformed to task parallel constructs like PROCESSES block and PROCESSDO loop of Fortran M. Also, For the case which program can be paralleized both PROCESSES block and PROCESSDO loop, we analyze that which construct is more effective for various conditions.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.383-386
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• 2009

In this paper, we propose some parallel structures of the word-based nonlinear combine functions in word-based stream cipher, high-speed versions of general (bit-based) nonlinear combine functions. Especially, we propose the high-speed structures of popular three kinds in word-based nonlinear combiners using by PS-WFSR (Parallel-Shifting or Parallel-Structured Word-based FSR): m-parallel word-based nonlinear combiner without memory, m-parallel word-based nonlinear combiner with memories, and m-parallel word-based nonlinear filter function. Finally, we analyze its cryptographic security and performance.

• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.1-10
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• 2004

A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.7
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• pp.213-218
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• 2015

Given two strings X and Y (|X|=m, |Y|=n) over an alphabet ${\Sigma}$, the extended edit distance between X and Y can be computed using dynamic programming in O(mn) time and space. Recently, a parallel algorithm that takes O(m+n) time and O(mn) space using m threads to compute the extended edit distance between X and Y was presented. In this paper, we present an improved parallel algorithm using the shared memory on GPU. The experimental results show that our parallel algorithm runs about 19~25 times faster than the previous parallel algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.337-342
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• 2010

In this paper, a new architecture for digit-parallel/bit-serial GF($2^m$) multiplier with low complexity is proposed. The proposed multiplier operates in polynomial basis of GF($2^m$) and produces multiplication results at a rate of one per D clock cycles, where D is the selected digit size. The digit-parallel/bit-serial multiplier is faster than bit-serial ones but with lower area complexity than bit-parallel ones. The most significant feature of the digit-parallel/bit-serial architecture is that a trade-off between hardware complexity and delay time can be achieved. But the traditional digit-parallel/bit-serial multiplier needs extra hardware for high speed. In this paper a new low complexity efficient digit-parallel/bit-serial multiplier is presented.