• 제목/요약/키워드: low-voltage applications

검색결과 751건 처리시간 0.042초

A Thermoelectric Energy Harvesting Circuit For a Wearable Application

  • Pham, Khoa Van;Truong, Son Ngoc;Yang, Wonsun;Min, Kyeong-Sik
    • 전기전자학회논문지
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    • 제21권1호
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    • pp.66-69
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    • 2017
  • In recent year, energy harvesting technologies from the ambient environments such as light, motion, wireless waves, and temperature again a lot of attraction form research community [1-5] due to its efficient solution in order to substitute for conventional power delivery methods, especially in wearable together with on-body applications. The drawbacks of battery-powered characteristic used in commodity applications lead to self-powered, long-lifetime circuit design. Thermoelectric generator, a solid-state sensor, is useful compared to the harvesting devices in order to enable self-sustained low-power applications. TEG based on the Seebeck effect is utilized to transfer thermal energy which is available with a temperature gradient into useful electrical energy. Depending on the temperature difference between two sides, amount of output power will be proportionally delivered. In this work, we illustrated a low-input voltage energy harvesting circuit applied discontinuous conduction mode (DCM) method for getting an adequate amount of energy from thermoelectric generator (TEG) for a specific wearable application. With a small temperature gradient harvested from human skin, the input voltage from the transducer is as low as 60mV, the proposed circuit, fabricated in a $0.6{\mu}m$ CMOS process, is capable of generating a regulated output voltage of 4.2V with an output power reaching to $40{\mu}W$. The proposed circuit is useful for powering energy to battery-less systems, such as wearable application devices.

저전압용 CMOS 온-칩 기준 전압 및 전류 회로 (CMOS on-chip voltage and current reference circuits for low-voltage applications)

  • 김민정;이승훈
    • 전자공학회논문지C
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    • 제34C권4호
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    • pp.1-15
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    • 1997
  • This paper proposes CMOS on-chip voltage and current reference circuits that operate at supply voltages between 2.5V and 5.5V without using a vonventional bandgap voltage structure. The proposed reference circuits based on enhancement-type MOS transistors show low cost, compatibility with other on-chip MOS circuits, low-power consumption, and small-chip size. The prototype was implemented in a 0.6 um n-well single-poly double-metal CMOS process and occupies an active die area of $710 um \times 190 um$. The proposed voltage reference realizes a mean value of 0.97 V with a standard deviation of $\pm0.39 mV$, and a temperature coefficient of $8.2 ppm/^{\circ}C$ over an extended temeprature range from TEX>$-25^{\circ}C$ to $75^{\circ}C$. A measured PSRR (power supply rejection ratio) is about -67 dB at 50kHz.

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Electrical Applications of OTFTs

  • Kim, Seong-Hyun;Koo, Jae-Bon;Lim, Sang-Chul;Ku, Chan-Hoi;Lee, Jung-Hun;Zyung, Tae-Hyoung
    • 한국고분자학회:학술대회논문집
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    • 한국고분자학회 2006년도 IUPAC International Symposium on Advanced Polymers for Emerging Technologies
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    • pp.170-170
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    • 2006
  • [ ${\pi}-conjugated$ ] organic and polymeric semiconductors are receiving considerable attention because of their suitability as an active layer for electronic devices. An organic inverter with a full swing and a high gain can be obtained through the good qualities of the transfer characteristics of organic thin-film transistors (OTFTs); for example, a low leakage current, a threshold voltage ($V_{th}$) close to 0 V, and a low sub-threshold swing. One of the most critical problems with traditional organic inverters is the high operating voltage, which is often greater than 20 V. The high operating voltage may result in not only high power consumption but also device instabilities such as hysteresis and a shift of $V_{th}$ during operation. In this paper, low-voltage and little-hysteresis pentacene OTFTs and inverters in conjunction with PEALD $Al_{2}O_{3}\;and\;ZrO_{2}$ as the gate dielectrics are demonstrated and the relationships between the transfer characteristics of OTFT and the voltage transfer characteristics (VTCs) of inverter are investigated.

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플라즈마 원자층증착법에 의해 제조된 강유전체 SrBi2Ta2O9박막의 특성 (Characteristics of Ferroelectric SrBi2Ta2O9 Thin Films deposited by Plasma-Enhanced Atomic Layer Deposition)

  • 신웅철;류상욱;유인규;윤성민;조성목;이남열;유병곤;이원재;최규정
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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    • pp.35-35
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    • 2003
  • Recent progress in the integration of the ferroelectric random access memories (FRAM) has attracted much interest. Strontium bismuth tantalate(SBT) is one of the most attractive materials for use in nonvolatile-memory applications due to low-voltage operations, low leakage current, and its excellent fatigue-free property. High-density FRAMs operated at a low voltage below 1.5V are applicable to mobile devices operated by battery. SBT films thinner than 0.1 #m can be operated at a low voltage, because the coercive voltage (Vc) decreases as the film thickness is reduced. In addition, the thickness of the SBT film will have to be reduced so it can fit between adjacent storage nodes in a pedestal type capacitor in future FRAMs.

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A Multi-Stage CMOS Charge Pump for Low-Voltage Memories

  • Lim, Gyu-Ho;Yoo, Sung-Han;Kim, Young-Hee
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2002년도 춘계종합학술대회
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    • pp.283-287
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    • 2002
  • To remedy both the degradation and saturation of the output voltages in the modified Dickson pump. a new multi-stage charge pump circuit is presented in this paper. Here using PMOS charge-transfer switches instead of NMOS ones eliminates the necessity of diode-configured output stage in the modified-Dickson pump, achieving the improved voltage pumping gain and its output voltages proportional to the stage numbers. Measurement indicates that VOUT/3VDD of this new pump circuit with two stages reaches to a value as high as 0.94 even with low VDD=1.0 V, strongly addressing that this scheme is very favorable at low-voltage memory applications.

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팬구동용 저압 8/6 SRM의 설계 및 구동 특성 (Design and Drive Characteristics of Low Voltage 8/6 SRM for Fan Application)

  • 안진우
    • 전기학회논문지
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    • 제63권10호
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    • pp.1371-1376
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    • 2014
  • In this paper, 4-phase switched reluctance motor(SRM) with 8-stator and 6-rotor pole structure is proposed for a high speed fan with a low voltage. The air blower has unidirectional rotation characteristics and requires a low torque ripple and noise as well as high efficiency. To achieve the requirements, voltage and current according to loading condition of limited specification is considered. Design process is to select the bore diameter, pole arc, york of stator and rotor to get a high torque and efficiency. To verify the validity of the proposed structure, finite element method(FEM) is employed to get the performances. And the converter for the proposed SRM is employed a 1.5q power converter for cost effectiveness. Prototype SRM is manufactured and tested, and the test results show this design is within the specification and good for the air blower applications.

산업용 저전압 SR모터의 진상각 제어 (Advance Angle Control For Industrial Low Voltage SR Motor)

  • 박대섭;신두진;허욱열
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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    • pp.232-232
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    • 2000
  • switched reluctance motors and drives are increasingly used in industrial applications due to their robust mechanical structure, low inertia and reduction in the rotor losses. As the motor speed increase turn on angle must be advanced to build up phase current. When C-dump converter is applied to switched reluctance motor, the capacitance of dump C has to have proper value. In this paper advance angle for a switched reluctance motor and capacitance of dump C are investigated. Then proper advance angle and the capacitance of dump-C are propose for the industrial low voltage SR motor.

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동기 스위치 제어를 통한 영전압 동작 고효율 능동 클램프 포워드 컨버터 (High Efficiency Active Clamp Forward Converter with Synchronous Switch Controlled ZVS Operation)

  • 이성세;최성욱;문건우
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2005년도 전력전자학술대회 논문집
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    • pp.266-268
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    • 2005
  • A new synchronous switch controlled transient current build-up zero voltage switching (TCB-ZVS) forward converter is proposed. The proposed converter is suitable for the low-voltage and high-current applications. The features of the proposed converter are low conduction loss of magnetizing current, no additional circuit for the ZVS operation, high efficiency, high power density and low EMI noise throughout all load conditions.

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A Ripple-free Input Current Interleaved Converter with Dual Coupled Inductors for High Step-up Applications

  • Hu, Xuefeng;Zhang, Meng;Li, Yongchao;Li, Linpeng;Wu, Guiyang
    • Journal of Power Electronics
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    • 제17권3호
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    • pp.590-600
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    • 2017
  • This paper presents a ripple-free input current modified interleaved boost converter for high step-up applications. By integrating dual coupled inductors and voltage multiplier techniques, the proposed converter can reach a high step-up gain without an extremely high turn-ON period. In addition, a very small auxiliary inductor employed in series to the input dc source makes the input current ripple theoretically decreased to zero, which simplifies the design of the electromagnetic interference (EMI) filter. In addition, the voltage stresses on the semiconductor devices of the proposed converter are efficiently reduced, which makes high performance MOSFETs with low voltage rated and low resistance $r_{DS}$(ON) available to reduce the cost and conduction loss. The operating principles and steady-state analyses of the proposed converter are introduced in detail. Finally, a prototype circuit rated at 400W with a 42-50V input voltage and a 400V output voltage is built and tested to verify the effectiveness of theoretical analysis. Experimental results show that an efficiency of 95.3% can be achieved.

A Nano-power Switched-capacitor Voltage Reference Using MOS Body Effect for Applications in Subthreshold LSI

  • Zhang, Hao;Huang, Meng-Shu;Zhang, Yi-Meng;Yoshihara, Tsutomu
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제14권1호
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    • pp.70-82
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    • 2014
  • A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in $0.18{\mu}m$ standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is $17.6ppm/^{\circ}C$, and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately $0.03mm^2$.