• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

• Journal of Sensor Science and Technology
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• v.30 no.1
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• pp.15-19
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• 2021

Image processing is one of the major techniques that are used for computer vision. Nowadays, researchers are using machine learning and deep learning for the aforementioned task. In recent years, digit recognition tasks, i.e., automatic meter recognition approach using electric or water meters, have been studied several times. However, two major issues arise when we talk about previous studies: first, the use of the deep learning technique, which includes a large number of parameters that increase the computational cost and consume more power; and second, recent studies are limited to the detection of digits and not storing or providing detected digits to a database or mobile applications. This paper proposes a system that can detect the digital number of meter readings using a lightweight deep neural network (DNN) for low power consumption and send those digits to an Android mobile application in real-time to store them and make life easy. The proposed lightweight DNN is computationally inexpensive and exhibits accuracy similar to those of conventional DNNs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.503-510
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• 2006

Readout circuit is to convert signal occurred in a defector into suitable signal for image signal processing. In general, it has to possess functions of impedance matching with perception element, amplification, noise reduction and cell selection. It also should satisfies conditions of low-power, low-noise, linearity, uniformity, dynamic range, excellent frequency-response characteristic, and so on. The technical issues in developing image processing equipment for focal plane way (FPA) can be categorized as follow: First, ultraviolet (UV) my detector material and fine processing technology. Second, ReadOut IC (ROIC) design technology to process electric signal from detector. Last, package technology for hybrid bonding between detector and ROIC. ROIC enables intelligence and multi-function of image equipment. It is a core component for high value added commercialization ultimately. Especially, in development of high-resolution image equipment ROIC, it is necessary that high-integrated and low-power circuit design technology satisfied with design specifications such as detector characteristic, signal dynamic range, readout rate, noise characteristic, ceil pitch, power consumption and so on. In this paper, we implemented a $8\times8$ FPA prototype ROIC for reduction of period and cost. We tested unit block and overall functions of designed $8\times8$ FPA ROIC. Also, we manufactured ROIC control and image boards, and then were able to verify operation of ROIC by confirming detected image from PC's monitor through UART(Universal Asynchronous Receiver Transmitter) communication.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.58-70
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• 1997

In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

• Journal of the Korea Society of Computer and Information
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• v.16 no.1
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• pp.1-9
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• 2011

Recently, as mobile multimedia devices are used more and more, the needs for high-performance and low-energy multimedia processors are increasing. Application-specific integrated circuits (ASIC) can meet the needed high performance for mobile multimedia, but they provide limited, if any, generality needed for various application requirements. DSP based systems can used for various types of applications due to their generality, but they require higher cost and energy consumption as well as less performance than ASICs. To solve this problem, this paper proposes a single instruction multiple data (SIMD) based many-core processor which supports high-performance and low-power image data processing while keeping generality. The proposed SIMD based many-core processor composed of 16 processing elements (PEs) exploits large data parallelism inherent in image data processing. Experimental results indicate that the proposed SIMD-based many-core processor higher performance (22 times better), energy efficiency (7 times better), and area efficiency (3 times better) than conversional commercial high-performance processors.

• IEMEK Journal of Embedded Systems and Applications
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• v.16 no.5
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• pp.233-240
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• 2021

We propose a novel, highly accurate approximate multiplier using different types of inexact 4-2 compressors. The importance of low hardware costs leads us to develop approximate multiplication for error-resilient applications. Several rules are developed when selecting a topology for designing the proposed multiplier. Our highly accurate multiplier design considers the different error characteristics of adopted compressors, which achieves a good error distribution, including a low relative error of 0.02% in the 8-bit multiplication. Our analysis shows that the proposed multiplier significantly reduces power consumption and area by 45% and 26%, compared with the exact multiplier. Notably, a trade-off relationship between error characteristics and hardware costs can be achieved when considering those of existing highly accurate approximate multipliers. In the image blending, edge detection and image sharpening applications, the proposed 8-bit approximate multiplier shows better performance in terms of image quality metrics compared with other highly accurate approximate multipliers.

• Journal of The Korean Astronomical Society
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• v.27 no.2
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• pp.191-201
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• 1994

We propose to use the entropy of power spectra defined in the frequency domain for the deconvolution of extended images. Spatial correlations requisite for extended sources may be insured by increasing the role of power entropy because the power is just a representation of spatial correlations in the frequency domain. We have derived a semi-analytical solution which is found to severely reduce computing time compared with other iteration schemes. Even though the solution is very similar to the well-known Wiener filter, the regularizingng term in the new expression is so insensitive to the noise characteristics as to assure a stable solution. Applications have been made to the IRAS $60{\mu}m\;and\;100{\mu}m$ images of the dark cloud B34 and the optical CCD image of a solar active region containing a circular sunspot and a small pore.

• Journal of KIISE
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• v.43 no.11
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• pp.1298-1306
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• 2016

Backlight has a major factor in power consumption of TFT-LCDs which are most popular in portable devices. There have been a lot of attempts to achieve power savings by backlight dimming. At the same time, the researches have shown image compensation due to decreased brightness of a displayed image. However, existing image compensation methods such as histogram equalization have some limits in completely satisfying the human visual system (HVS)-awareness. This paper proposes an enhanced dimming technique to obtain both power saving and HVS-awareness by combining pixel compensation and histogram specification for TFT-LCDs. This method executes a search algorithm and an automation algorithm employing simplified calculations for fast image processing. Experimental results showed that the proposed method achieved significant improvement in visual satisfaction per power saving over existing backlight dimming.

• Journal of IKEEE
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• v.22 no.4
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• pp.1214-1217
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• 2018

In this paper, we propose the development of a Small $360^{\circ}$ Oral Scanner embedded board. The proposed small $360^{\circ}$ oral scanner embedded board consists of image level and transfer method changing part FPGA part, memory part and FIFO to USB transfer part. The image level and transmission mode change unit divides the MIPI format oral image received through the small $360^{\circ}$ oral cavity image sensor and the image sensor into low power signal mode and high speed signal mode and distributes them to the port and transfers the level shift to the FPGA unit. The FPGA unit performs functions such as $360^{\circ}$ image distortion correction, image correction, image processing, and image compression. In the FIFO to USB transfer section, the RAW data transferred through the FIFO in the FPGA is transferred to the PC using USB 3.0, USB 3.1, etc. using the transceiver chip. In order to evaluate the efficiency of the proposed small $360^{\circ}$ oral scanner embedded board, it has been tested by an authorized testing institute. As a result, the frame rate per second is over 60 fps and the data transfer rate is 4.99 Gb/second

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.12
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• pp.11-19
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• 1999

Fractal image compression algorithm has been studied mostly not in the view of hardware but software. However, a general processor by software can't decode fractal compressed images in real-time. Therefore, it is necessary that we develop a fast dedicated hardware. However, design examples of dedicated hardware are very rare. In this paper, we designed a quadtree fractal-based compressed image decoder which can decode $256{\times}256$ gray-scale images in real-time and used two power-down methods. The first is a hardware-optimized simple post-processing, whose role is to remove block effect appeared after reconstruction, and which is easier to be implemented in hardware than non-2' exponents weighted average method used in conventional software implementation, lessens costs, and accelerates post-processing speed by about 69%. Therefore, we can expect that the method dissipates low power and low energy. The second is to design a power dissipation in the multiplier can be reduced by about 28% with respect to a general array multiplier which is known efficient for low power design in the size of 8 bits or smaller. Using the above two power-down methods, we designed decoder's core block in 3.3V, 1 poly 3 metal, $0.6{\mu}m$ CMOS technology.