• Journal of Electrical Engineering and Technology
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• v.11 no.6
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• pp.1700-1706
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• 2016

In this paper, a dual-stator, spoke-type linear vernier machine (DSSLVM) for wave energy extraction application was proposed. This machine is capable of producing a competitively high thrust force and force density at a low operation speed in direct drive systems. The operation principal and working of the proposed DSSLVM were studied. The stator core height is adjusted to improve the overall force density of the proposed machine while reducing the force ripple. To evaluate the advantages of the proposed DSSLVM, the main performance was compared with that of a recently developed linear primary permanent magnet vernier machine (LPPMVM). The proposed machine exhibited greater thrust force and force density, an improved power factor and lower force ripple with the same permanent magnet (PM) volume compared to the LPPMVM.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1335-1336
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• 2007

Among the emerging non-volatile memory technologies, phase change memories are the most attractive in terms of both performance and scalability perspectives. Phase-change random access memory(PRAM), compare with flash memory technologies, has advantages of high density, low cost, low consumption energy and fast response speed. However, PRAM device has disadvantages of set operation speed and reset operation power consumption. In this paper, we investigated scalability of $Ge_{1}Se_{1}Te_{2}$ chalcogenide material to improve its properties. As a result, reduction of phase change region have improved electrical properties of PRAM device.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.940-948
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• 2008

This paper presents a low-power, low-complexity design and implementation results of a high speed multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN (WLAN) baseband processor. The proposed processor is composed of the physical layer convergence procedure (PLCP) processor and physical medium dependent (PMD) processor, which have been optimized to have low-power and reduced-complexity architecture. It was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. As a result, the proposed TX-PLCP processor reduced the power consumption by as much as 81% over the bit-level operation architecture. Also, the proposed MIMO symbol detector reduced the hardware complexity by 18% over the conventional SQRD-based architecture with division circuits and square root operations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.89-93
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• 2007

This paper presents the design and the implementation of input/output (I/O) interface circuits for 2.5 Gbps operation in a 3.3V 0.35um CMOS technology. Due to the differential transmission technique and low voltage swing, LVDS(low-voltage differential signaling) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS standard. The LVDS proposed in this paper utilizes a telescopic amplifier. This circuit is operated up to 2.3 Gbps. The circuit has a power consumption of 25. 5mW. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.476-478
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• 2006

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. In this paper a 64/65, 128/129 dual-modulus prescaler is designed using a $0.25{\mu}m$ CMOS process. In the design a new dynamic D-flip flop is employed, where glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The designed prescaler operates up to 2.5GHz and consumes 3.1mA at 2.5GHz operation.

• Proceedings of the KSR Conference
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• 2011.10a
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• pp.3007-3018
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• 2011

This paper describes how to apply to commutate of thyristor efficiently. Thyristor is used for the high power system, as the research to secure domestic technology of the Current Source Inverter(CSI) for the synchronous motor operation which is used for the propulsion system of KTX. It has been composed to be available for the stable switching operation of the thyristor by supplementing problem of load commutation method, according to small Counter ElectricMotive Force(EMF) at low speed area of synchronous motor, via auxiliary commutation circuit using forced commutation method. We also have verified through the simulation using the Matlab.

• Journal of IKEEE
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• v.19 no.3
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• pp.288-294
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• 2015

CRC function has been built into the high-speed semiconductor memory device in order to increase the reliability of data for high-speed operation. Also, DBI function is adopted to improve of data transmission speed. Conventional CRC(ATM-8 HEC code) method has a significant amounts of area-overhead(~XOR 700 gates), and processing time(6 stage XOR) is large. Therefore it leads to a considerable burden on the timing margin at the time of reading and writing of the low power memory devices for CRC calculations. In this paper, we propose a CRC method for low cost and high speed memory, which was improved 92% for area-overhead. For low-cost implementation of the CRC scheme by the DBI function it was supplemented by data bit error detection rate. And analyzing the error detection rate were compared with conventional CRC method.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.3
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• pp.234-240
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• 2007

In this paper, a novel multi-level inverter for low cost high speed switched reluctance(SR) drive is proposed. The proposed multi-level converter has reduced number of power switches and diodes than that of a conventional asymmetric converter for SRM and smaller voltage rating of the dump capacitor comparing with energy efficient c-dump converter. It can supply five operating modes that is boosted, DC-link, zero, negative bias and negative boosted voltage. The proposed multi-level converter has fast excitation and demagnetization modes of phase current, so dynamic response can be achieved. The proposed multi-level converter is verified by computer simulation and experimental results.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3184-3186
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• 1999

In this paper, a new structure of fully differential delay cell VCO using quadrature phase for low phase noise and high speed operation is suggested. It is realized by inserting voltage clamp circuit into input pairs of delay cells that include three-control current source having high output impedance. In this reason. this newly designed delay cell for VCO has the low power supply sensitivity so that the phase noise can be reduced. The whole characteristics of VCO were simulated by using HSPICE and SABER. Simulation results show that the phase noise of new VCO is quite small compared with conventional fully differential delay cell VCO and ring oscillator type VCO. It is also very beneficial to low power supply design because of wide tuning range.

• Magazine of the Korean Society of Agricultural Engineers
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• v.18 no.4
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• pp.4259-4264
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• 1976

This paper, is about the test on the operating performance of diesel engine by using of soybean oil which farmers could supply in their farm yard. The diesel engine used is a swirl-chamber type, four stroke cycle with single cylinder, air cooling and its rated horse power is 2 PS per 1300 rpm. Several results obtained are as follows; 1. The starting performance of diesel engine with soybean oil is almost the same as that with light oil. 2. The variation of engine speed according to various engine load is small when soybean oil is used compared with light oil. It is considered that soybean oil is desirable for the purpose of industerial power machine fuel. 3. The specific fuel consumption increases approximately 10 percent high in the condition of rated horse power and maximum horse power and shows less or same during the load test in low velocity, when soybean oil is used 4. Though the brake thermal efficiency in the condition of rated horse power and maximum horse power is inclined to decrease when soybean oil is used compared during the load test in low velocityt shows good inclination.