• 전기학회논문지P
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• 제65권4호
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• pp.298-302
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• 2016

Currently, logistics are in small quantities and in diverse forms, and the amounts are continuously increasing. Railway logistics however are losing their market share every year mainly due to low operation speed and loading time, which means the trucks are covering the most of the freights. In order to solve these situations, this paper proposed the high speed freight train as working multi-modality with other modes to make effective transshipment. The high speed freight train has maximum operation speed of 300km/h and electric power to run centralized power supply. There are large dual door system, bogie system covering fluctuating load of 15[ton], automatic loading device, ULD(unit load device) bed and ULD locking system in this freight rolling stock. We calculated the performance of powering and braking capacity for this train and proposed how many vehicles are composed of train set. The results in this paper can help to make a decision to define the technical specification of High-speed freight train for the efficiency of rail freight service.

• 전자공학회논문지C
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• 제34C권4호
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• pp.16-25
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• 1997

This paper shows a SDRAM opeating in 200MHz clock cycle which it use data interleave and pipelining for high speed operation. We proposed NdC (Negative DEaly circuit) to improve clock to access time(tAC) characteristics, also we proposed low power WL(wordline)driver circit and high efficiency VPP charge-pump circit. Our all circuits has been fabricated using 0.4um CMOS process, and the measured maximum speed is 200Mbytes/s in LvTTL interface.

• 대한전자공학회논문지SD
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• 제46권7호
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• pp.1-6
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• 2009

본 논문은 DRAM에서 DBI (Data Bus Inversion)를 이용한 새로운 방식의 High Speed 아키텍쳐를 설명하고자한다. DBI는 SSO와 LSI와 같은 잘 알려진 문제를 감소시키기 위한 방식중의 하나이다. 본 논문에서는 Analog Majority Voter(AMV), DBI Flag에 의한 GIO 제어회로, 새로운 SSO Algorithm과 같은 많은 아키텍쳐들이 Data Bus의 천이(Toggle) 개수를 줄이기 위해서 제안되었다. DBI Flag에 의해 GIO데이터 반전 여부를 결정되기 때문에 파워 소모가 감소될 수 있고, 데이터 Eye diagram도 40ps이상 증가될 수 있게 되었다. 제안된 DBI Scheme을 이용하였을 때 High speed 동작에서 거의 안정한 SI특성을 얻을 수 있게 됐다. 90nm CMOS Technology를 이용하여 제조되었다.

• 한국초전도ㆍ저온공학회논문지
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• 제8권1호
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• pp.26-28
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• 2006

The development technique of digital logic using CMOS device is close reached several limitations These make technical needs that are ultra high speed superconductive systems based on CMOS silicon digital computing technique. Comparing digital logic based on silicon CMOS, the computing technique based on ultra high speed superconductive systems has many advantages which are ultra low power consumption, ultra high operation speed. etc. It is estimated that features like these increasingly improve the possibility of ultra low power and ultra superconductive systems. In this paper digital logics of current CMOS technique and RSFQ superconductive technique are compared with and analyzed.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제49권2호
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• pp.102-109
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• 2000

The magnetically levitated system technology is highly expected to contribute the new transportation system of the 21st century with its high velocity operation, better riding comforts, friendliness to environment and saving of maintenance labour. Its development has been completed in low speed and in high speed application. In 2005, the Transrapid with 430 km/h speed will go into operation between Berlin and Hamburg[1]. In the year 2000, the realization of JR-Maglev will be basically evaluated for commercial operation[2]. In korea, maglev test vehicle with magnet for levitation and single sided linear induction motor for propulsion is under test at 1 [km] test track in KIMM.[3,4] Here, a transverse flux linear motor in combination with the levitation and the guidance leads to a considerable high power density and high efficiency simultaneously. The designed and measured performance of transverse flux linear motor for maglev system revealed a great potential of system mass reduction.

• 전력전자학회논문지
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• 제20권5호
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• pp.429-436
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• 2015

Torque ripples generate mechanical vibration at low speed and acoustic noise at high speed. The back emf harmonics of a PM synchronous motor is one of the main sources of torque ripples. To reduce torque ripples resulting from back emf harmonics, dq-axis harmonic currents that reduce the torque ripples are generally compensated to the current controller. Harmonic current compensation is effective at low speed, but it is not applicable at high speed because of the limited bandwidth of the current controller. In this study, dq-axis harmonic voltage compensation that can reduce torque ripples at high speed is proposed. The dq-axis harmonic voltages are calculated from the motor speed and the dq-axis harmonic currents. The effectiveness of the proposed method in reducing torque ripple is verified by a simulation and experiments.

• Journal of Power Electronics
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• 제9권4호
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• pp.582-592
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• 2009

This paper proposes a new speed sensorless direct torque and flux controlled interior permanent magnet synchronous motor (IPMSM) drive. Closed-loop control of both the torque and stator flux linkage are achieved by using two proportional-integral (PI) controllers. The reference voltage vectors are generated by a SVM unit. The drive uses an adaptive sliding mode observer for joint stator flux and rotor speed estimation. Global asymptotic stability of the observer is achieved via Lyapunov analysis. At low speeds, the observer is combined with the high frequency signal injection technique for stable operation down to standstill. Hence, the sensorless drive is capable of exhibiting high dynamic and steady-state performances over a wide speed range. The operating range of the direct torque and flux controlled (DTFC) drive is extended into the high speed region by incorporating field weakening. Experimental results confirm the effectiveness of the proposed method.

• 전력전자학회논문지
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• 제10권2호
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• pp.186-193
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• 2005

본 논문에서는 산업체 CNC(Computer Numerical Control) 분야에서 사용되는 빌트인 타입 스핀들 모터를 구동하기 위한 기법을 제시하였다. 저속 영역에서 유리한 전류 모델과 고속 영역에서 유리한 전압 모델을 혼합해서 사용하는 고피나스 모델 자속추정기는 회전자 자속추정을 위하여 이용하였다. 그리고 약계자 제어를 사용하여 스핀들 모터를 고속 운전하였다. 시뮬레이션과 실험을 통해 약계자 영역에서의 스핀들 모터 고속운전을 확인하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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• pp.430-433
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• 2003

IGBTS are widely used for the industrial inverters in the mid power range at low voltage (440V$\~$660V) application. Advantageous features of the device are simple gate drive and high speed switching capability. Due to these advantages the application of IGBTS is enlarging into the high power application. However, to increase the power handling capacity at lower input voltage level, the current rating in each bridge arm must be enlarged. Therefore the parallel operation of IGBT devices is essentially needed. This paper describes the feasible parallel structures of the power circuit for the mid & the high power inverters and introduces the important design condition for the parallel operation of IGBT devices. To verify feasibility of the IGBT parallel operation, the feature of several IGBT devices (EUPEC, SEMIKRON's IGBT) are investigated and the power stacks are implemented and tested with these devices. The experimental results show the good characteristics for the parallel operation of IGBTS.

• Journal of Power Electronics
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• 제12권1호
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• pp.49-57
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• 2012

This paper presents performance evaluation of an Integrated Starter-Alternator (ISA) prototype with an Interior Permanent Magnet (IPM) synchronous machine under sensor-less operation. To attain a high starting torque at zero speed and in subsequent extremely low speed range, a hybrid signal injection method is proposed. At higher speed, an improved stator flux observer is used for the stator flux estimation. This observer is able to produce accurately-estimated stator flux linkage for high performance Direct Torque and Flux Control (DTFC) implementation. The sensor-less DTFC IPM synchronous machine drive takes full advantage of the capacity of the power converter and fulfills the control specifications for the ISA. The trajectory control algorithm responds rapidly and in a well behaved manner over a wide range of operating conditions. The experimental results verify the feasibility and advantages of the system.