• 한국정보통신학회논문지
• /
• 제13권12호
• /
• pp.2633-2640
• /
• 2009

본 논문에서는 터치스크린 컨트롤러용 IC를 위한 저면적, 저전력, 고속 EEPROM 회로 설계기술을 제안하였다. 저면적 EEPROM 기술로는 SSTC (Side-wall Selective Transistor Cell) 셀을 제안하였고 EEPROM 코어회로에서 반복되는고전압 스위칭 회로를 최적화하였다. 저전력 기술은 디지털 Data Bus 감지 증폭기 회로를 제안하였다. 그리고 고속 EEPROM 기술로는 Distributed DB 방식이 적용되었으며, Dual Power Supply를 사용하여 EEPROM 셀과 고전압 스위칭 회로의 구동전압은 로직전압 VDD(=1.8V)보다 높은 전압인 VDDP(=3.3V)를 사용하였다. 설계된 128Kb EEPROMIP(Intellectual Property)의 레이아웃 면적은 $662.31{\mu}m{\times}1314.89{\mu}m$이다.

• 대한전자공학회논문지SD
• /
• 제42권2호
• /
• pp.41-48
• /
• 2005

본 논문은 기존의 CVSL 전가산기 회로 내부에 Low-Swing 기술의 특성을 갖도록 NMOS 트랜지스터를 추가하여 감소된 출력전압으로 동작하는 CVSL 전가산기를 제안하였다. 또한 제안한 Low-Swing CVSL 전가산기를 이용하여 $8\times8$ 병렬 곱셈기를 구성한 후 회로의 성능을 평가하였다. 본 논문에서 제안한 Low-Swing CVSL 전가산기 회로는 $13.1\%$의 전력감소와 $14.3\%$의 전력소모와 지연시간의 곱(power-delay-product) 감소가 이루어졌다 Hynix $0.35{\mu}m$ 표준 CMOS 공정을 사용하여 HSPICE로 시뮬레이션하고 그 동작 특성을 검증하였다.

• Journal of Korean Vacuum Science & Technology
• /
• 제3권1호
• /
• pp.66-73
• /
• 1999

In this paper, the design of one-chip FED system integrated with driving circuits in reported on the basis of MOSFET controlled FEA (MCFEA). To integrate a MOSFET with a FEA efficiently, a new fabrication process is proposed. It is confirmed that the MOSFET with threshold voltage of about 2volts controls the FEA emission current up to 20 ${\mu}$A by applying driving voltage of 15 volts, which is enough current level to utilize the MCFEA as a pixel for FED. The drain breakdown voltage of the MOSFET is measured to be 70 volts, which is also high enough for 60 volt operation of FED. The circuits for row and column driver are designed stressing on saving area, reducing malfunction probability and consuming low power to maximize the merit of on-chip driving circuits. Dynamic logic concept and bootstrap capacitors are used to meet these requirements. By integrating the driving circuit with FEA, the number of external I/O lines can be less than 20, irrespectively of the number of pixels.

• 전자공학회논문지C
• /
• 제34C권12호
• /
• pp.1-8
• /
• 1997

In this paper, a new method of state code assignment for reduction of switching activities of state transition in asynchronous circuits is proposed. The algorithm is based on a on-hot code and modifies it to reduce switching activities. To estimate switching activities as a cost functions we introduce state transition probability (STP). AS a results, the proposed algorithm has an advantage of 60% over with the conventional code assignment in terms of switching and code length of state assignment.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.301-304
• /
• 2001

The analog multiplier is very useful building block in many circuits such as filter, frequency-shifter, and modulators. In recent year, The main design issue of circuit designer is low-voltage/low-power system design, because of all systems are recommended very integrated system and portable system In this paper, the proposed the four-quadrant analog multiplier is using the bulk-driven techniques. The bulk-driven technique is very useful technique in low-voltage system, compare with gate-driven technique. therefore the proposed analog multiplier is operated in 1V supply voltage. And the proposed analog multiplier is low power dissipation compare with the others. therefor the proposed analog multiplier is convenient in low-voltage/low-power in system.

• 한국전기전자재료학회논문지
• /
• 제31권4호
• /
• pp.261-266
• /
• 2018

When the clamp meter approaches the electric path where current is flowing, leakage current can be measured at a distance from the electric current because the induced current increases as the magnitude of the current increases and approaches nearer to the electric path. Therefore, measurements were carried out from a distance to avoid this effect. In addition, the measured values differ depending on the location of the power line that penetrates the ZCT of the clamp meter, thus measurements were performed at a location where this effect was minimized. The fraction of compliant branch circuits, whose leakage current was lower than 1.00 mA, was found to be 69.0% out of the total of 439 branch circuits, while the percentage of compliant branch circuits having an insulation resistance higher than $0.20M{\Omega}$ was found to be 93.2%. The reason why the percentage of compliant branch circuits with low leakage current was low might be due to the inclusion of capacitive leakage current in the total measured leakage current.

• 대한의용생체공학회:학술대회논문집
• /
• 대한의용생체공학회 1990년도 추계학술대회
• /
• pp.118-121
• /
• 1990

This paper describes development of an implantable power switching system for biotelemetry system. This system is designed and manufactured to achieve as small size and low power dissipation as possible, using pulse powered circult and CMOS technology. The function of the power switching system is to connect the implantable battery to implanted sensors and, electronics systems by receiving intermittent command signals from external circuits. The power dissipation of this system was about $15{\mu}W$ for a stand-by operation.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
• /
• pp.69-74
• /
• 2004

System-on-glass technology made with low temperature poly-Si TFT has been rapidly advancing in recent years. We have developed a low-power, narrow edged frame, 1.9inch system-on-glass LCD which fully integrates a 16-bit RGB interface driver and all power circuits required for driving the LCD. In this paper, the latest poly-Si TFT circuit technologies used in the newly developed LCD are discussed. The development trends are also reviewed.

• 한국정보통신설비학회:학술대회논문집
• /
• 한국정보통신설비학회 2006년도 하계학술대회
• /
• pp.179-182
• /
• 2006

This paper introduce a different-type voltage-controlled oscillator (VCO) for PLL frequency synthesizer, And also the architecture of a high speed low-power-consumption CMOS dual-modulus frequency divider is presented. It provides a new approach to high speed operation and low power consumption. The proposed circuits simulate in 0.35 um CMOS standard technology.

• ETRI Journal
• /
• 제37권1호
• /
• pp.97-106
• /
• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).