• International Journal of Computer Science & Network Security
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• v.21 no.1
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• pp.137-142
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• 2021

The Internet of Things (IoT) paradigm is at the forefront of present and future research activities. The huge amount of sensing data from IoT devices needing to be processed is increasing dramatically in volume, variety, and velocity. In response, cloud computing was involved in handling the challenges of collecting, storing, and processing jobs. The fog computing technology is a model that is used to support cloud computing by implementing pre-processing jobs close to the end-user for realizing low latency, less power consumption in the cloud side, and high scalability. However, it may be that some resources in fog computing networks are not suitable for some kind of jobs, or the number of requests increases outside capacity. So, it is more efficient to decrease sending jobs to the cloud. Hence some other fog resources are idle, and it is better to be federated rather than forwarding them to the cloud server. Obviously, this issue affects the performance of the fog environment when dealing with big data applications or applications that are sensitive to time processing. This research aims to build a fog topology job scheduling (FTJS) to schedule the incoming jobs which are generated from the IoT devices and discover all available fog nodes with their capabilities. Also, the fog topology job placement algorithm is introduced to deploy jobs into appropriate resources in the network effectively. Finally, by comparing our result with the state-of-art first come first serve (FCFS) scheduling technique, the overall execution time is reduced significantly by approximately 20%, the energy consumption in the cloud side is reduced by 18%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.8
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• pp.1102-1108
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• 2020

Mobile edge computing is a technology that can prepare for a new era of cloud computing and compensate for shortcomings by processing data near the edge of the network where data is generated rather than centralized data processing. It is possible to realize a low-latency/high-speed computing service by locating computing power to the edge and analyzing data, rather than in a data center far from computing and processing data. In this article, we develop a virtual mobile edge computing testbed environment where the cloud and edge nodes divide computing tasks from mobile terminals using the EdgeCloudSim simulator. Performance of offloading techniques for distribution of computing tasks from mobile terminals between the central cloud and mobile edge computing nodes is evaluated and analyzed under the virtual mobile edge computing environment. By providing a virtual mobile edge computing environment and offloading capabilities, we intend to provide prior knowledge to industry engineers for building mobile edge computing nodes that collaborate with the cloud.

• Journal of Korea Multimedia Society
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• v.23 no.1
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• pp.31-42
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• 2020

During the 4th Industrial Revolution, service platforms utilizing diverse contents are emerging, and research on recommended systems that can be customized to users to provide quality service is being conducted. hybrid recommendation systems that provide high accuracy recommendations are being researched in various domains, and various filtering techniques, machine learning, and deep learning are being applied to recommended systems. However, in a recommended service environment where data must be analyzed and processed real time, the accuracy of the recommendation is important, but the computational speed is also very important. Due to high level of model complexity, a hybrid recommendation system or a Deep Learning-based recommendation system takes a long time to calculate. In this paper, a Cascade-hybrid recommended algorithm is proposed that can reduce the computational time while maintaining the accuracy of the recommendation. The proposed algorithm was designed to reduce the complexity of the model and minimize the computational speed while processing sequentially, rather than using existing weights or using a hybrid recommendation technique handled in parallel. Therefore, through the algorithms in this paper, contents can be analyzed and recommended effectively and real time through services such as SNS environments or shared economy platforms.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.44-57
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• 2016

Rectification is used as a preprocessing to reduce the computation complexity of disparity estimation. However, rectification also requires a complex computation. To minimize the computing complexity, rectification using a lookup-table (R-LUT) has been introduced. However, since, the R-LUT consumes large amount of memory, rectification with compressed LUT (R-CLUT) has been introduced. However, the more we reduce the memory consumption, the more we need decoding overhead. Therefore, we need to attain an acceptable trade-off between the size of LUT and decoding overhead. In this paper, we present such a trade-off by adaptively combining simple coding methods, such as differential coding, modified run-length coding (MRLE), and Huffman coding. Differential coding is applied to transform coordinate data into a differential form in order to further improve the coding efficiency along with Huffman coding for better stability and MRLE for better performance. Our experimental results verified that our coding scheme yields high performance with maintaining robustness. Our method showed about ranging from 1 % to 16 % lower average inverse of compression ratio than the existing methods. Moreover, we maintained low latency with tolerable hardware overhead for real-time implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.25-34
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• 2012

This paper presents a universal architecture for variable-length eight-parallel Reed-Solomon (RS) decoder for high-rate WPAN systems. The proposed architecture can support not only RS(255,239) code but various shortened RS codes. Moreover, variable-length architecture provides variable low latency for various shortened RS codes and the eight-parallel design also provides high data processing rate. Using 90-$nm$ CMOS standard cell technology, the proposed RS decoder has been synthesized and measured for performance. The proposed RS decoder can provide a maximum 19-$Gbps$ data rate at clock frequency 300 $MHz$.

• Journal of Korea Multimedia Society
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• v.19 no.8
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• pp.1487-1497
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• 2016

Explosively growing service of digital multimedia data increases the need for highly scalable low-cost storage. This paper proposes the new storage architecture based on torus network which does not need network switch and erasure coding for efficient storage usage for high scalability and efficient disk utilization. The proposed model has to compensate for the disadvantage of long network latency and network processing overhead of torus network. The proposed storage model was compared to two most popular distributed file system, GlusterFS and Ceph distributed file systems through a prototype implementation. The performance of prototype system shows outstanding results than erasure coding policy of two file systems and mostly even better results than replication policy of them.

• KIPS Transactions on Software and Data Engineering
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• v.12 no.9
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• pp.399-406
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• 2023

Cloud computing has been evolved to support edge computing architecture that combines fog management layer with edge servers. The main reason why it is received much attention is low communication latency for real-time IoT applications. At the same time, various cloud task scheduling techniques based on artificial intelligence have been proposed. Artificial intelligence-based cloud task scheduling techniques show better performance in comparison to existing methods, but it has relatively high scheduling time. In this paper, we propose a deep learning-based dynamic scheduling with multi-agents supporting scalability in edge computing environments. The proposed method shows low scheduling time than previous artificial intelligence-based scheduling techniques. To show the effectiveness of the proposed method, we compare the performance between previous and proposed methods in a scalable experimental environment. The results show that our method supports real-time IoT applications with low scheduling time, and shows better performance in terms of the number of completed cloud tasks in a scalable experimental environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.10
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• pp.539-549
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• 2002

PC cluster-based Information Retrieval (IR) systems improve their performances by parallel processing of query terms using cluster nodes. However TCP/IP based communication used to exchange data between cluster nodes prevents the performance from being improved further. The user-level communication mechanisms solve the problem by eliminating the time-consuming kernel access in exchanging data between cluster nodes. The Virtual Interface Architecture (VIA) is one of the representative user-level communication mechanisms which provide low latency and high bandwidth. In this paper, we propose a VIA-based parallel IR system on a PC cluster. The IR system is implemented using the following three communication methods: Sealable Coherent Interface (SCI) based VIA, MPI on SCI based VIA, MPI on Fast Ethernet based VIA. Through experiments, the performances of the three methods are analyzed in various aspects.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.186-191
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• 2019

In this paper, we propose a implementation approach of the high-speed feature extraction algorithm. The proposed method is based on the block type classification algorithm which reduces the computation time when target macro block is divided to smooth block type that has no image features. It is quantitatively identified that occurs at 29.5% of the total image using 200 standard test images with $64{\times}64$ macro block size. This means that within a standard test image containing various image information, 29.5% can reduce the complexity of the operation. When the proposed approach is applied to the Canny edge detection, the required latency of the edge detection can be completely eliminated, such as 2D derivative filter, gradient magnitude/direction computation, non-maximal suppression, adaptive threshold calculation, hysteresis thresholding. Also, it is expected that operation time of the feature detection can be reduced by applying block type classification algorithm to various feature extraction algorithms in this way.