• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.112-118
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• 2014

As higher quality of image is required for digital image scaling, longer processing time is required. Therefore the technology that can make higher quality image quickly is needed. We propose the double linear-cubic convolution interpolation which creates the high quality image with low complexity and hardware resources. The proposed interpolation methods which are made up of four one-dimensional linear interpolations and one one-dimensional cubic convolution perform linear-cubic convolution interpolation in horizontal and vertical direction. When compared in aspects of peak signal-to-noise ratio(PSNR), performance time and amount of hardware resources, the proposed interpolation provided better PSNR, low complexity and less hardware resources than bicubic convolution interpolation.

• The Journal of the Acoustical Society of Korea
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• v.29 no.1
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• pp.18-23
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• 2010

The RLS (Recursive Least Squares) method is a broadly used adaptive algorithm for signal processing in electronic engineering. The RLS algorithm shows a good performance and a fast adaptation within a stationary environment, but it shows a Poor performance within a non-stationary environment because the method has a fixed forgetting factor. In order to enhance 'tracking' performances, BLS methods with an adaptive forgetting factor had been developed. This method shows a good tracking performance, however, it suffers from heavy computational loads. Therefore, we propose a modified AFF-RLS which has relatively low complexity m this paper.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.4
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• pp.156-163
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• 1996

In this paper, we described the implementation and the sound quality assessment of a real-time stereo audio codec using TMS320C40 DSP (digital signal processing) chip for low bitrte and high quality audio. We implemented hardware and software in order to overcome a real-time processing problem of audio compression algorithm that can be produced by largely recursive computing and complexity of the process. We have studied five types of distortion that can be produced by perceptual coding and the codec was evaluated by eight test musics that are selected in SQAM (sound quality assessment material) 422-2-4-2 produced by EBU (european broadcast union). The subjective listening tests were carried out on the codec quality and preformance by double blind method in a listening room with eleven listeners. As a result, 5 grade-impairment scale was scored under minus one and the codec quality was evaluated to be perceptible, but not annoying.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.4
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• pp.414-418
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• 2016

In this paper, a hardware architecture of low area gradient magnitude calculator is proposed. For the hardware complexity reduction, the characteristic of orthogonal projection vector and hardware resource sharing technique are applied. The proposed hardware architecture can be implemented without degradation of the gradient magnitude data quality since the proposed hardware is implemented with original algorithm. The FPGA implementation result shows the 15% of logic elements and 38% embedded multiplier savings compared with previous work using Altera Cyclone VI (EP4CE115F29C7N) FPGA and Quartus II v15.0 environment.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.3
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• pp.226-231
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• 2010

This paper proposes a new coding technique for constructing error correcting high rate DC-free multimode code using a generator matrix generated from a sparse parity-check matrix. The scheme exploits high rate generator matrixes for producing distinct candidate codewords. The decoding complexity depends on whether the syndrome of the received codeword is zero or not. If the syndrome is zero, the decoding is simply performed by expurgating the redundant bits of the received codeword. Otherwise, the decoding is performed by a sum-product algorithm. The performance of the proposed scheme can achieve a reasonable DC-suppression and a low bit error rate.

• Journal of the Institute of Convergence Signal Processing
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• v.22 no.1
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• pp.38-44
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• 2021

Wi-Fi provides some low-power connection solutions that other Bluetooth cannot provide, and at the same time brings many benefits. First, there is a potentially higher data rate: it can reach 230mbps. Wi-Fi coverage is also wider than competitors, and its operating frequency is also 5GHz, which is much less congested than 2.4GHz. Finally, it also supports IP networks, which is important if you want to send data to the cloud without complexity. The 802.11ac standard of the previous generation still accounts for most shipments (80.9%) and revenue (76.2%). However, there is a limit to accepting IoT devices that will continue to increase significantly in the future. To solve this problem, the new Wi-Fi 6 standard is expected to be the solution (IEEE 802.11ax) which is quickly becoming the main driving force of the wireless local area network (WLAN) market. According to IDC market research analysts, in the first quarter of 2020, independent access points (APs) supported by Wi-Fi 6 accounted for 11.8% of shipments, but 21.8% of revenue. In this paper, we have compared and analyzed the IoT connectivity, QoS, and security requirements of devices using Wi-Fi 6 network.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.3
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• pp.158-163
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• 2009

LMS(Least Mean Square) algorithm requires simple equation and is used widely because of the low complexity. If the convergence speed increase, LMS algorithm has a divergence in case of sharp environment changes. And if a stability increase, the convergence speed becomes slow. This algorithm based on a trade off between fast convergence and system stability. To improve this problem, VSSLMS (Variable Step Size LMS) algorithm was developed. The VSSLMS algorithm improved the convergence speed and performance as adjusting step size using error signal. In this paper, I-VSSLMS algorithm is proposed tor improve the performance of adaptive noise canceller in real-time environments. The proposed algorithm is applied to adaptive noise canceller using TMS320C6713 DSP board and we did simulation by real time. Then we compared performance of each algorithm and demonstrated that proposed algorithm has superior performance.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.10 no.2
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• pp.192-197
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• 2017

In this paper, image filter optimization method based on common sub-expression elimination is proposed for low-power image feature extraction hardware design. Low power and high performance object recognition hardware is essential for industrial robot which is used for factory automation. However, low area Gaussian gradient filter hardware design is required for object recognition hardware. For the hardware complexity reduction, we adopt the symmetric characteristic of the filter coefficients using the transposed form FIR filter hardware architecture. The proposed hardware architecture can be implemented without degradation of the edge detection data quality since the proposed hardware is implemented with original Gaussian gradient filtering algorithm. The expremental result shows the 50% of multiplier savings compared with previous work.

• Journal of Information Processing Systems
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• v.15 no.3
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• pp.604-615
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• 2019

Single-user spectrum sensing is susceptible to multipath effects, shadow effects, hidden terminals and other unfavorable factors, leading to misjudgment of perceived results. In order to increase the detection accuracy and reduce spectrum sensing cost, we propose an adaptive cooperative sensing strategy based on an estimated signal-to-noise ratio (SNR). Which can adaptive select different sensing strategy during the local sensing phase. When the estimated SNR is higher than the selection threshold, adaptive double threshold energy detector (ED) is implemented, otherwise cyclostationary feature detector is performed. Due to the fact that only a better sensing strategy is implemented in a period, the detection accuracy is improved under the condition of low SNR with low complexity. The local sensing node transmits the perceived results through the control channel to the fusion center (FC), and uses voting rule to make the hard decision. Thus the transmission bandwidth is effectively saved. Simulation results show that the proposed scheme can effectively improve the system detection probability, shorten the average sensing time, and has better robustness without largely increasing the costs of sensing system.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.57-66
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• 2014

This paper presents a low-complexity barrel distortion correction processor for wide-angle cameras. The proposed processor performs the barrel distortion correction jointly with the color demosaicking, so that the hardware complexity can be reduced significantly. In addition, to reduce the required memory bandwidth, an efficient memory interface is proposed by utilizing the spatial locality of the memory access in the correction process. The proposed processor is implemented with 35K logic gates in a $0.11-{\mu}m$ CMOS process and its correction speed is 150 Mpixels/s at the operating frequency of 606MHz, where the supported frame size is $2048{\times}2048$ and the required memory bandwidth is 1 read/cycle.