• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.447-448
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• 2008

This paper presents a low-complexity design and implementation results of a multi-input multi-output (MIMO) orthogonal frequency division multiplexing (OFDM) symbol detector for high speed wireless LAN (WLAN) systems. The proposed spatial division multiplexing (SDM) symbol detector is designed by HDL and synthesized to gate-level circuits using 0.18um CMOS library. The total gate count for the symbol detector is 238K.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2015년도 제46회 하계학술대회
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• pp.1339-1340
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• 2015

In this paper, we propose a low-complexity control scheme for segway. To design the controller, we use the prescribed performance function and analyze the stability of the proposed control system using the Lyapunov stability theorem. By prescribed performance function, we can adjust the transient and steady-state response. Finally, the simulation results are provided to illustrate the effectiveness of the proposed scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.488-496
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• 2016

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

• 전자공학회논문지
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• 제53권12호
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• pp.42-49
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• 2016

논문은 저면적 비트-직렬 두 최소값 생성기를 제안한다. Min-sum 복호 알고리즘을 적용한 LDPC 복호기에서 두 최소값 생성기가 가장 큰 하드웨어 복잡도를 가지기 때문에, 두 최소값 생성기의 저면적 구현이 매우 중요하다. 하드웨어 면적을 줄이기 위해 비트-직렬 방식의 LDPC 복호기가 제안되었다. 하지만 기존의 비트-직렬 방식의 생성기는 하나의 최소값만 찾을 수 있어 BER 성능이 감소되었다. 제안하는 생성기는 두 최소값을 모두 찾을 수 있어 BER 성능열화를 극복하고 저면적의 LDPC 복호기 구현이 가능하다. 또한 기존의 두 최소값 생성기들과 비교하여 면적-시간 복잡도에서 가장 좋은 성능을 보인다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권3호
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• pp.293-299
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• 2016

Recently, as IoT (Internet of Things) becomes more important, low cost implementation of sensor nodes also becomes critical issues for two well-known standards, IEEE 802.15.4 and IEEE 802.15.6 which stands for WPAN (Wireless Personal Area Network) and WBAN (Wireless Body Area Network), respectively. This paper presents the area-optimized AES-CCM (Advanced Encryption Standard - Counter with CBC-MAC) hardware security engine which can support both IEEE 802.15.4 and IEEE 802.15.6 standards. First, for the low cost design, we propose the 8-bit AES encryption core with the S-box that consists of fully combinational logic based on composite field arithmetic. We also exploit the toggle method to reduce the complexity of design further by reusing the AES core for performing two operation mode of AES-CCM. The implementation results show that the total gate count of proposed AES-CCM security engine can be reduced by up to 42.5% compared to the conventional design.

• 한국통신학회논문지
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• 제39C권8호
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• pp.637-642
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• 2014

본 논문은 블록 LDPC(low density parity check) 부호 설계를 위한 순환 천이 값(shift index)을 탐색하는 효율적인 알고리즘을 제안한다. 여기에는 메시지-패싱(message-passing) 기반의 순환 주기(cycle) 탐색 알고리즘과 ACE(approximate cycle extrinsic message degree) 알고리즘이 결합되어 있다. LDPC 부호 성능에 영향을 미치는 요인들에 우선순위를 두어 효율적으로 순환 천이 값을 찾을 수 있도록 했다. 이 알고리즘을 통해 기존의 탐색 알고리즘 보다 훨씬 낮은 복잡도로 행렬 저장 공간을 절약하면서 좋은 성능의 패리티 검사 행렬(parity check matrix)을 만들 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.427-435
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• 2015

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

• ETRI Journal
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• 제40권2호
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• pp.218-226
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• 2018

Multiuser detection (MUD) and channel estimation techniques in space-division multiple-access aided orthogonal frequency-division multiplexing systems recently has received intensive interest in receiver design technologies. The maximum likelihood (ML) MUD that provides optimal performance has the cost of a dramatically increased computational complexity. The minimum mean-squared error (MMSE) MUD exhibits poor performance, although it achieves lower computational complexity. With almost the same complexity, an MMSE with successive interference cancellation (SIC) scheme achieves a better bit error rate performance than a linear MMSE multiuser detector. In this paper, hybrid ML-MMSE with SIC adaptive multiuser detection based on the joint channel estimation method is suggested for signal detection. The simulation results show that the proposed method achieves good performance close to the optimal ML performance at low SNR values and a low computational complexity at high SNR values.

• Journal of Information Processing Systems
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• 제2권3호
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• pp.153-158
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• 2006

In this paper, we propose an image interpolator for low computational complexity. The proposed image interpolator supports the image scaling using a modified cubic convolution interpolation between the input and output resolutions for a full screen display. In order to reduce the computational complexity, we use the difference in value of the adjacent pixels for selecting interpolation methods and linear function of the cubic convolution. The proposed image interpolator is compared with the conventional one for the computational complexity and image quality. The proposed image interpolator has been designed and verified by Verilog HDL(Hardware Description Language). It has been synthesized using the Xilinx VirtexE FPGA, and implemented using an FPGA-based prototype board.

• 한국멀티미디어학회논문지
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• 제14권10호
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• pp.1238-1242
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• 2011

An efficient architecture for the reduction of complexity in forward quantization of H.264/AVC is presented in this paper. Since the multiplication operation in forward quantization plays crucial role in complexity of algorithm. More efficient quantization architecture with simplified high speed multiplier is proposed. It uses the modification of the quantization operation and the high speed multiplier is applied for simplification of quantization process.