JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Low-Complexity Non-Iterative Soft-Decision BCH Decoder Architecture for WBAN Applications

  • Jung, Boseok (Dept. of Information and Communication Engr. Inha University) ;
  • Kim, Taesung (Dept. of Information and Communication Engr. Inha University) ;
  • Lee, Hanho (Dept. of Information and Communication Engr. Inha University)
  • Received : 2015.10.27
  • Accepted : 2016.03.14
  • Published : 2016.08.30
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Abstract

This paper presents a low-complexity non-iterative soft-decision Bose-Chaudhuri-Hocquenghem (SD-BCH) decoder architecture and design technique for wireless body area networks (WBANs). A SD-BCH decoder with test syndrome computation, a syndrome calculator, Chien search and metric check, and error location decision is proposed. The proposed SD-BCH decoder not only uses test syndromes, but also does not have an iteration process. The proposed SD-BCH decoder provides a 0.75~1 dB coding gain compared to a hard-decision BCH (HD-BCH) decoder, and almost similar coding gain compared to a conventional SD-BCH decoder. The proposed SD-BCH (63, 51) decoder was designed and implemented using 90-nm CMOS standard cell technology. Synthesis results show that the proposed non-iterative SD-BCH decoder using a serial structure can lead to a 75% reduction in hardware complexity and a clock speed 3.8 times faster than a conventional SD-BCH decoder.

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References

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