• 제목/요약/키워드: low-area design

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UHF RFID 태그 칩용 저전력, 저면적 256b EEPROM IP 설계 (Design of a Low-Power and Low-Area EEPROM IP of 256 Bits for an UHF RFID Tag Chip)

  • 강민철;이재형;김태훈;장지혜;하판봉;김영희
    • 한국정보통신학회:학술대회논문집
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    • 한국해양정보통신학회 2009년도 춘계학술대회
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    • pp.671-674
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    • 2009
  • 본 논문에서는 수동형 UHF RFID 태그 칩에 사용되는 저전력, 저면적 256b 비동기식 EEPROM을 설계 하였다. 먼저 EEPROM의 저전력 특성을 얻기 위해 1.8V의 공급전압을 사용하였고, 저전압 특성을 갖는 N-type Schottky Diode를 사용하여 Dickson Charge pump를 설계하였다. 그리고 주변회로에서의 저면적 설계를 위해 비동기식 인터페이스 방식과 Separate I/O 방식을 사용하였다. 그리고 DC-DC 변환기의 면적을 줄이기 위하여 Schottky Diode를 사용한 Dickson Charge Pump를 설계하였다. $0.18{\mu}m$ EEPROM 공정을 이용하여 설계된 16 행 ${\times}$ 16 열의 어레이를 갖는 256b EEPROM의 레이아웃 면적은 $311.66{\times}490.59{\mu}m^2$이다.

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A Low-area and Low-power 512-point Pipelined FFT Design Using Radix-24-23 for OFDM Applications

  • Yu, Jian;Cho, Kyung-Ju
    • 한국정보전자통신기술학회논문지
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    • 제11권5호
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    • pp.475-480
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    • 2018
  • In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.

Area-Optimized Multi-Standard AES-CCM Security Engine for IEEE 802.15.4 / 802.15.6

  • Choi, Injun;Kim, Ji-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권3호
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    • pp.293-299
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    • 2016
  • Recently, as IoT (Internet of Things) becomes more important, low cost implementation of sensor nodes also becomes critical issues for two well-known standards, IEEE 802.15.4 and IEEE 802.15.6 which stands for WPAN (Wireless Personal Area Network) and WBAN (Wireless Body Area Network), respectively. This paper presents the area-optimized AES-CCM (Advanced Encryption Standard - Counter with CBC-MAC) hardware security engine which can support both IEEE 802.15.4 and IEEE 802.15.6 standards. First, for the low cost design, we propose the 8-bit AES encryption core with the S-box that consists of fully combinational logic based on composite field arithmetic. We also exploit the toggle method to reduce the complexity of design further by reusing the AES core for performing two operation mode of AES-CCM. The implementation results show that the total gate count of proposed AES-CCM security engine can be reduced by up to 42.5% compared to the conventional design.

비동기 설계 방식기반의 저전력 뉴로모픽 하드웨어의 설계 및 구현 (Low Power Neuromorphic Hardware Design and Implementation Based on Asynchronous Design Methodology)

  • 이진경;김경기
    • 센서학회지
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    • 제29권1호
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    • pp.68-73
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    • 2020
  • This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

광복로 로드숍 파사드디자인의 색채분석을 통한 지역색 연구 (A Study on Area Color of Gwangbok-ro Based on the Analysis of the Colors of the Facade Designs of Stores Along the Road)

  • 여미;이창노
    • 한국실내디자인학회논문집
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    • 제22권1호
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    • pp.247-255
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    • 2013
  • In this study, the colors and characteristics of Gwangbok-ro of Busan were analyzed in the standpoint of local images based on the examination of the facade designs of stores along the road of Gwangbok-ro, Busan a main street with massive population flow. To that end, the facades of stores, correlation with the city, color and locality were examined, and after the status of facade designs in Gwangbok-ro were identified through case survey by it, color images were analyzed. For color analysis, Munsell color system was used as basic tool. As a result of examining the colors in Gwangbok-ro area, the following status could be analyzed on 3 attributes of hue, brightness and chroma: First, analysis results of hue indicated that dominant color that covers 70% or more of the area represented mid brightness and low chroma in GY(36.1%) series, subsidiary color which covers 25% or more of the area mid brightness and low chroma in YR(26.5%) series, and accent color that covers less than 5% of the area high brightness and low chroma of GY(40%) series. Second, in brightness analysis, dominant color mostly represented mid brightness, subsidiary color mid brightness and accent color high brightness respectively. In particular accent color showed more intensive crowding phenomenon in high brightness. Third, as for chroma, dominant color, subsidiary color and accent color all are gathered in low chroma, however in small number of accent colors, peculiar high chroma appeared notable. In conclusion, the colors of Gwangbok-ro area analyzed based on the facade design of the stores along the road in this study were superficial colors that reflect the life of people in the area, artificial colors by improvement of the local environment. This study is meaningful in that the image of Gwangbok-ro was found through building colors in one part of the city Busan. It is judged that the study results would become useful as reference document in planning out environment colors later on.

TCSC의 $H_{\infty}$ 제어에 의한 대규모 전력계통의 지역간 저주파진동 억제 Part II: $H_{\infty}$제어기 설계 (Damping Inter-area Low Frequency Oscillations in Large Power Systems with $H_{\infty}$ Control of TCSC PARTII: Design of $H_{\infty}$ Controller)

  • 김용구;전영환;송성근;심관식;남해곤
    • 대한전기학회논문지:전력기술부문A
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    • 제49권5호
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    • pp.233-241
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    • 2000
  • This paper presents a systematic design procedure of $H_{\infty}$ controller of TCSC for damping low frequency inter-area oscillations in large power systems. Sensitivities of the inter-area mode for changes in line susceptance are computed using the eigen-sensitivity theory of augmented system matrix and TCSC locations are selected using the line sensitivities. The reduced model required for designing a manageable-size $H_{\infty}$ controller is obtained using the reduced frequency domain system identification method and the various weighting functions are tuned systematically to provide a robust performance. The proposed $H_{\infty}$ controller proved to be very effective for damping the inter-area mode of the large KEPCO power system.

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개인 무선 통신을 위한 868/915MHz SoC 시스템 구조 설계 (Design of 868/915MHz SoC System Architecture for Wireless Personal Area Network)

  • 박주호;오정열;고영준;길민수;김재영
    • 대한임베디드공학회논문지
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    • 제2권1호
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    • pp.24-30
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    • 2007
  • According to development of wireless communication technologies, we need not only high data rate but low data rate system of low power consumption. This low data rate system is utilized in the field of home automation, health care, sensoring and monitoring, etc. IEEE 802.15.4 LR-WPAN system is the best choice for realizing ubiquitous networking system. In this paper SoC Architecture for IEEE 802.15.4 Low Rate WPAN is designed. IEEE 802.15.4 Low Rate WPAN system serves the functions and realization of home area network. We propose the SoC architecture for 868/915MHz frequency band of IEEE 802.15.4 Low Rate WPAN system. The key issue is to design SoC architecture which provides the function of Low Rate WPAN system to meet the requirement of IEEE 802.15.4 standards.

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새로운 고속의 NCL 셀 기반의 지연무관 비동기 회로 설계 (Delay Insensitive Asynchronous Circuit Design Based on New High-Speed NCL Cells)

  • 김경기
    • 한국산업정보학회논문지
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    • 제19권6호
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    • pp.1-6
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    • 2014
  • 지연 무관방식의 NCL 비동기 설계는 혁신적인 비동기 회로 설계 방식의 하나로써 견고성, 소비전력 그리고 용이한 설계의 재사용과 같은 많은 장접을 가지고 있다. 그러나, 기존의 NCL 게이트 셀들의 트랜지스터-레벨 구조들은 느린 스피드, 높은 영역 오버헤드, 높은 와이어(wire) 복잡도와 같은 약점 또한 가지고 있다. 따라서, 본 논문에서는 빠른 스피드, 낮은 영역 오버헤드, 낮은 와이더 복잡도를 위해서 트랜지스터 레벨에서 설계된 새로운 고속의 NCL 게이트 셀을 제안하고자 한다. 제안된 고속의 NCL 게이트 셀들은 회로 지연, 영역, 소모 전력에 의해서 기존의 다른 NCL 게이트 셀들과 비교되었다..

저전력 고속 NCL 비동기 게이트 설계 (Design of Low Power and High Speed NCL Gates)

  • 김경기
    • 전자공학회논문지
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    • 제52권2호
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    • pp.112-118
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    • 2015
  • 기존의 동기방식의 회로는 나노미터 영역에서의 공정, 전압, 온도 변이 (PVT variation), 그리고 노화의 영향으로 시스템의 전체 성능을 유지할 수 없을 뿐만 아니라 올바른 동작을 보장할 수도 없다. 따라서 본 논문에서는 여러 가지 변이에 영향을 받지 않는 비동기회로 설계 방식 중에서 타이밍 분석이 요구되지 않고, 설계가 간단한 DI(delay insentive) 방식의 NCL (Null Convention Logic) 설계 방식을 이용하여 디지털 시스템을 설계하고자 한다. 기존의 NCL 게이트들의 회로 구조들은 느린 스피드, 높은 영역 오버헤드, 높은 와이어(wire) 복잡도와 같은 약점을 가지고 있기 때문에 본 논문에서는 빠른 스피드, 낮은 영역 오버헤드, 낮은 와이더 복잡도를 위해서 트랜지스터 레벨에서 설계된 새로운 저전력 고속 NCL 게이트 라이브러리를 제안하고자 한다. 제안된 NCL 게이트들은 동부 0.11um 공정으로 구현된 비동기 방식의 곱셈기의 지연, 소모 전력에 의해서 기존의 NCL 게이트 들과 비교되었다.

Simulated tropical cyclonic winds for low cycle fatigue loading of steel roofing

  • Henderson, David J.;Ginger, John D.;Morrison, Murray J.;Kopp, Gregory A.
    • Wind and Structures
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    • 제12권4호
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    • pp.383-400
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    • 2009
  • Low rise building roofs can be subjected to large fluctuating pressures during a tropical cyclone resulting in fatigue failure of cladding. Following the damage to housing in Tropical Cyclone Tracy in Darwin, Australia, the Darwin Area Building Manual (DABM) cyclic loading test criteria, that loaded the cladding for 10000 cycles oscillating from zero to a permissible stress design pressure, and the Experimental Building Station TR440 test of 10200 load cycles which increased in steps to the permissible stress design pressure, were developed for assessing building elements susceptible to low cycle fatigue failure. Recently the 'Low-High-Low' (L-H-L) cyclic test for metal roofing was introduced into the Building Code of Australia (2007). Following advances in wind tunnel data acquisition and full-scale wind loading simulators, this paper presents a comparison of wind-induced cladding damage, from a "design" cyclone proposed by Jancauskas, et al. (1994), with current test criteria developed by Mahendran (1995). Wind tunnel data were used to generate the external and net pressure time histories on the roof of a low-rise building during the passage of the "design" cyclone. The peak pressures generated at the windward roof corner for a tributary area representative of a cladding fastener are underestimated by the Australian/New Zealand Wind Actions Standard. The "design" cyclone, with increasing and decreasing wind speeds combined with changes in wind direction, generated increasing then decreasing pressures in a manner similar to that specified in the L-H-L test. However, the L-H-L test underestimated the magnitude and number of large load cycles, but overestimated the number of cycles in the mid ranges. Cladding elements subjected to the L-H-L test showed greater fatigue damage than when experiencing a five hour "design" cyclone containing higher peak pressures. It is evident that the increased fatigue damage was due to the L-H-L test having a large number of load cycles cycling from zero load (R=0) in contrast to that produced during the cyclone.