• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.671-674
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• 2009

We design a low-power and low-area asynchronous EEPROM of 256 bits used in a passive UHF RFID tag chip. For a low-power solution, we use a supply voltage of 1.8V and design a Dickson charge pump using N-type Schottky diodes with a low-voltage characteristic. And we use an asynchronous interface and a separate I/O method for a low-area solution of the peripheral circuit of the designed EEPROM. And we design a Dickson charge pump using N-type Schottky diodes to reduce an area of DC-DC converter. The layout area of the designed EEPROM of 256 bits with an array of 16 rows and 16 columns using $0.18{\mu}m$ EEPROM process is $311.66{\times}490.59{\mu}m^2$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.11 no.5
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• pp.475-480
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• 2018

In OFDM-based systems, FFT is a critical component since it occupies large area and consumes more power. In this paper, we present a low hardware-cost and low power 512-point pipelined FFT design method for OFDM applications. To reduce the number of twiddle factors and to choose simple design architecture, the radix-$2^4-2^3$ algorithm are exploited. For twiddle factor multiplication, we propose a new canonical signed digit (CSD) complex multiplier design method to minimize the hardware-cost. In hardware implementation with Intel FPGA, the proposed FFT design achieves more than about 28% reduction in gate count and 18% reduction in power consumption compared to the previous approaches.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.293-299
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• 2016

Recently, as IoT (Internet of Things) becomes more important, low cost implementation of sensor nodes also becomes critical issues for two well-known standards, IEEE 802.15.4 and IEEE 802.15.6 which stands for WPAN (Wireless Personal Area Network) and WBAN (Wireless Body Area Network), respectively. This paper presents the area-optimized AES-CCM (Advanced Encryption Standard - Counter with CBC-MAC) hardware security engine which can support both IEEE 802.15.4 and IEEE 802.15.6 standards. First, for the low cost design, we propose the 8-bit AES encryption core with the S-box that consists of fully combinational logic based on composite field arithmetic. We also exploit the toggle method to reduce the complexity of design further by reusing the AES core for performing two operation mode of AES-CCM. The implementation results show that the total gate count of proposed AES-CCM security engine can be reduced by up to 42.5% compared to the conventional design.

• Journal of Sensor Science and Technology
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• v.29 no.1
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• Korean Institute of Interior Design Journal
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• v.22 no.1
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• pp.247-255
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• 2013

In this study, the colors and characteristics of Gwangbok-ro of Busan were analyzed in the standpoint of local images based on the examination of the facade designs of stores along the road of Gwangbok-ro, Busan a main street with massive population flow. To that end, the facades of stores, correlation with the city, color and locality were examined, and after the status of facade designs in Gwangbok-ro were identified through case survey by it, color images were analyzed. For color analysis, Munsell color system was used as basic tool. As a result of examining the colors in Gwangbok-ro area, the following status could be analyzed on 3 attributes of hue, brightness and chroma: First, analysis results of hue indicated that dominant color that covers 70% or more of the area represented mid brightness and low chroma in GY(36.1%) series, subsidiary color which covers 25% or more of the area mid brightness and low chroma in YR(26.5%) series, and accent color that covers less than 5% of the area high brightness and low chroma of GY(40%) series. Second, in brightness analysis, dominant color mostly represented mid brightness, subsidiary color mid brightness and accent color high brightness respectively. In particular accent color showed more intensive crowding phenomenon in high brightness. Third, as for chroma, dominant color, subsidiary color and accent color all are gathered in low chroma, however in small number of accent colors, peculiar high chroma appeared notable. In conclusion, the colors of Gwangbok-ro area analyzed based on the facade design of the stores along the road in this study were superficial colors that reflect the life of people in the area, artificial colors by improvement of the local environment. This study is meaningful in that the image of Gwangbok-ro was found through building colors in one part of the city Busan. It is judged that the study results would become useful as reference document in planning out environment colors later on.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.5
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• pp.233-241
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• 2000

This paper presents a systematic design procedure of $H_{\infty}$ controller of TCSC for damping low frequency inter-area oscillations in large power systems. Sensitivities of the inter-area mode for changes in line susceptance are computed using the eigen-sensitivity theory of augmented system matrix and TCSC locations are selected using the line sensitivities. The reduced model required for designing a manageable-size $H_{\infty}$ controller is obtained using the reduced frequency domain system identification method and the various weighting functions are tuned systematically to provide a robust performance. The proposed $H_{\infty}$ controller proved to be very effective for damping the inter-area mode of the large KEPCO power system.

• IEMEK Journal of Embedded Systems and Applications
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• v.2 no.1
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• pp.24-30
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• 2007

According to development of wireless communication technologies, we need not only high data rate but low data rate system of low power consumption. This low data rate system is utilized in the field of home automation, health care, sensoring and monitoring, etc. IEEE 802.15.4 LR-WPAN system is the best choice for realizing ubiquitous networking system. In this paper SoC Architecture for IEEE 802.15.4 Low Rate WPAN is designed. IEEE 802.15.4 Low Rate WPAN system serves the functions and realization of home area network. We propose the SoC architecture for 868/915MHz frequency band of IEEE 802.15.4 Low Rate WPAN system. The key issue is to design SoC architecture which provides the function of Low Rate WPAN system to meet the requirement of IEEE 802.15.4 standards.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.6
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• pp.1-6
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• 2014

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of low speed, high area overhead or high wire complexity. Therefore, this paper proposes a new high-speed NCL gate cells designed at transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate cells have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.2
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• pp.112-118
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• 2015

Conventional synchronous circuits cannot keep the circuit performance, and cannot even guarantee correct operations under the influence of PVT variations and aging effects in the nanometer regime. Therefore, in this paper, a DI (delay insensitive) design based NCL (Null Convention Logic) design methodology with a very simple design structure has been used to design digital systems, which is one of well-known asynchronous design methods robust to various variations and does not require any timing analysis. Because circuit-level structures of conventional NCL gates have weakness of low speed, high area overhead or high wire complexity, this paper proposes a new lNCL gates designed at the transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate libraries have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption using a asynchronous multiplier implemented in dongbu 0.11um CMOS technology.

• Wind and Structures
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• v.12 no.4
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• pp.383-400
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• 2009

Low rise building roofs can be subjected to large fluctuating pressures during a tropical cyclone resulting in fatigue failure of cladding. Following the damage to housing in Tropical Cyclone Tracy in Darwin, Australia, the Darwin Area Building Manual (DABM) cyclic loading test criteria, that loaded the cladding for 10000 cycles oscillating from zero to a permissible stress design pressure, and the Experimental Building Station TR440 test of 10200 load cycles which increased in steps to the permissible stress design pressure, were developed for assessing building elements susceptible to low cycle fatigue failure. Recently the 'Low-High-Low' (L-H-L) cyclic test for metal roofing was introduced into the Building Code of Australia (2007). Following advances in wind tunnel data acquisition and full-scale wind loading simulators, this paper presents a comparison of wind-induced cladding damage, from a "design" cyclone proposed by Jancauskas, et al. (1994), with current test criteria developed by Mahendran (1995). Wind tunnel data were used to generate the external and net pressure time histories on the roof of a low-rise building during the passage of the "design" cyclone. The peak pressures generated at the windward roof corner for a tributary area representative of a cladding fastener are underestimated by the Australian/New Zealand Wind Actions Standard. The "design" cyclone, with increasing and decreasing wind speeds combined with changes in wind direction, generated increasing then decreasing pressures in a manner similar to that specified in the L-H-L test. However, the L-H-L test underestimated the magnitude and number of large load cycles, but overestimated the number of cycles in the mid ranges. Cladding elements subjected to the L-H-L test showed greater fatigue damage than when experiencing a five hour "design" cyclone containing higher peak pressures. It is evident that the increased fatigue damage was due to the L-H-L test having a large number of load cycles cycling from zero load (R=0) in contrast to that produced during the cyclone.