• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2007.05a
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• pp.265-270
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• 2007

The potential and step voltage distribution around low voltage joint-box cover were simulated with the variation of resistivity of water, depth of submerged water and point of leakage current. The potential distribution is very high gradient around low voltage joint-box, this condition is very dangerous states.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.4
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• pp.28-34
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• 2012

Installing surge protection devices for a low-voltage system is important to ensure the survival of electric or electronic devices and systems. If surge protection devices (SPD) are installed without consideration of the concept of lightning protection zones, the equipment to be protected might be damaged despite the correct energy coordination of SPDs. This damage is induced by the reflection phenomena on the cable connecting an external SPD and the load protected. These reflection phenomena depend on the characteristics of the output of the external SPD, the input of the loads, and the cables between the load and the external SPD. Therefore, the SPD has an effective protection distance under the condition of the specific load and the specific voltage protection level of SPD. In this paper, PSCAD/EMTDC software is used to simulate the residual voltage characteristics of SPD Entering the low-voltage device. And by applying a certain voltage level, the effective protection distances of SPD were analyzed according to the each load and length of connecting cable, and the effectiveness of SPD were verified.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.6
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• pp.586-590
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• 2006

This paper deals with the application of a partial discharge (PD) test on low-voltage electrical and electronic devices, which is recently being accepted as a non-destructive and a effective dielectric test method. A comparative analysis combined with the Withstand Voltage Test (WVT) specified in IEC standards was carried out on low-voltage insulation transformers. The results showed that the WVT causes insulation degradation of the specimen during the test by applying high voltage. However, the PD test can be performed in ranges from 30 % to 50 % of the test voltage specified in the WVT. Therefore, the PD test is successfully applicable for a non-destructive test method on low-voltage electrical and electronic devices as a replacement of the WVT.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.51 no.6
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• pp.285-291
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• 2002

In general, utility voltage is maintained at a relatively low level of Phase unbalance since a low level of unbalance can cause a significant power supply ripple and heating effects on the power system equipment. Voltage unbalance more commonly emerges in individual customer loads due to phase load unbalanced, especially where single phase power loads are used. Under unbalanced input voltages large lower order harmonics appears at the input and output ports of Power conversion devices. As the application of adjustable -speed drives (ASDs) and their integration with complex industrial processes increase, so does the need to understand how ASDs perform during voltage This paper describes a real load test to investigate the performance of 3-HP adjustable speed drives by an unbalanced voltage at the low-voltage system.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.707-710
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• 1998

This paper presents a new voltage down converter(VDC) for low power, high speed DRAM. This VDC Consists of RVG(Reference Voltage Generator) and Driver Circuit. And it is independent of temperature variation, and Supply Voltage. Using weak inversion region, this RVG dissipates low power. Internal Voltage Source of this VDC is stable in spite of high speed operation of memory array. This circuit is designed with a $0.65\mu\textrm{m}$ nwell CMOS technology. In HSPICE simulation results, Temperature dependency of this RVG is $20\muV/^{\circ}C,$ supply voltage dependency is $\pm0.17%,$ $VCC=3.3V\pm0.3V,$ and current dissipation is $5.22\muA.$ Internal voltage source bouncing of this VDC is smaller than conventional VDC.

• Journal of Power Electronics
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• v.9 no.3
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• pp.438-446
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• 2009

The performance of direct torque controlled (DTC) interior permanent magnet (IPM) machines is poor at low speeds due to a few reasons, namely limited accuracy of stator voltage acquisition and the presence of offset and drift components in the acquired signals. Due to factors such as forward voltage drop across switching devices in the three phase inverter and dead-time of the devices, the voltage across the machine terminals differ from the reference voltage vector used to estimate stator flux and electromagnetic torque. This can lead to instability of the IPM drive during low speed operation. Compensation schemes for forward voltage drops and dead-time are proposed and implemented in real-time control, resulting in improved performance of the space vector modulated DTC IPM drive, especially at low speeds. No additional hardware is required for these compensators.

• Journal of IKEEE
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• v.22 no.3
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• pp.716-722
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• 2018

This paper presents a voltage angle control strategy for surface permanent magnet synchronous motor (SPMSM) drives used in low-cost applications, wherein a current vector control is not employed. In the proposed method, the current vector control scheme, which requires high precision phase-current sensing units and a fast calculation capability of a motor drive controller, is replaced with the voltage angle controller. The proposed voltage angle controller calculates a d-axis voltage command to make the d-axis current zero by using a simple equation obtained from the voltage equation of SPMSM. The proposed method shows performance similar to the current vector controlled SPMSM drive during steady-states and its structure is very simple and thus it can be easily implemented with a low-cost microcontroller. The effectiveness of the proposed method is verified through simulations and experiments.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.5
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• pp.753-756
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• 2012

In this paper, a modified low-votlage CMOS bandgap voltage reference with CTAT compensation is presented. The proposed structure doesn't use PTAT current. The proposed structure is more simple than the existing structure and doesn't use the eighteen BJT. The modified low-votlage CMOS bandgap voltage reference with CTAT compensation has been successfully verified in a standard 0.18um CMOS process. The simulation results have confirmed that, with the minimum supply voltage of 1.25V, the output reference voltage at 549mV has a temperature coefficient of 12$ppm/^{\circ}C$ from $0^{\circ}C$ to $100^{\circ}C$.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.55 no.8
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• pp.416-422
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• 2006

With the increasing demand for renewable energy, distributed power included in fuel cells have been studied and developed as a future energy source. For this system, a power conversion circuit is necessary to interface the generated power to the utility. In many cases, a high step-up dc/dc converter is needed to boost low input voltage to high voltage output. Conventional methods using cascade dc/dc converters cause extra complexity and higher cost. The conventional topologies to get high output voltage use flyback dc/dc converters. They have the leakage components that cause stress and loss of energy that results in low efficiency. This paper presents a high boost converter with a voltage multiplier and a coupled inductor. The secondary voltage of the coupled inductor is rectified using a voltage multiplier and series-connected with the boost voltage of primary voltage of the coupled inductor. Therefore, high boost voltage is obtained with low duty cycle. Theoretical analysis and experimental results verify the proposed solutions using a 300W prototype.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.528-533
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• 2016

A low voltage high PSRR CMOS Bandgap circuit capable of generating a stable voltage of less than 1 V (0.8 V and 0.5 V) robust to Process, Voltage and Temperature (PVT) variations is proposed. The high PSRR of the circuit is guaranteed by a low-voltage current mode regulator at the central aspect of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage $V_{reg}$ for the BG core and Op-Amp rather than the VDD. These current mirrors reduce the impact of supply voltage variations. The proposed circuit is implemented in a $0.35{\mu}m$ CMOS technology. The BGR circuit occupies $0.024mm^2$ of the die area and consumes $200{\mu}W$ from a 5 V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference achieved -118 dB at frequencies up to 1 kHz and -55 dB at 1 MHz without additional circuits for the curvature compensation. A temperature coefficient of $60 ppm/^{\circ}C$ is obtained in the range of -40 to $120^{\circ}C$.