• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• Electrical & Electronic Materials
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• v.7 no.3
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• pp.225-230
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• 1994

In this paper, we have fabricated short channel MOSFETs with these parameters to verify the validity of process parameters extraction by DTC method. The experimental results of fabricated short channel devices according to the optimal process parameters demonstrate good device characteristics such as good drain current-voltage characteristics, low body effects and threshold voltage of$\leq$+-.1.0V, high punch through and breakdown voltage of$\leq$12V, low subthreshold swing(S.S) values of$\leq$105mV/decade.

• Journal of Sensor Science and Technology
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• v.33 no.1
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• pp.12-17
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• 2024

Floating inverter amplifiers (FIAs) have recently garnered considerable attention owing to their high energy efficiency and inherent resilience to input common-mode voltages and process-voltage-temperature variations. Since the voltage gain of a simple FIA is low, it is typically cascaded or cascoded to achieve a higher voltage gain. However, cascading poses stability concerns in closed-loop applications, while cascoding limits the output swing. This study introduces a gain-enhanced FIA that features cross-coupled body biasing. Through simulations, it is demonstrated that the proposed FIA designed using a 28-nm complementary metal-oxide-semiconductor technology with a 1-V power supply can achieve a high voltage gain (> 90 dB) suitable for dynamic open-loop applications. The proposed FIA can also be used as a closed-loop amplifier by adjusting the amount of positive feedback due to the cross-coupled body biasing. The capability of achieving a high gain with minimum-length devices makes the proposed FIA a promising candidate for low-power, high-speed sensor interface systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.89-93
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• 2007

This paper presents the design and the implementation of input/output (I/O) interface circuits for 2.5 Gbps operation in a 3.3V 0.35um CMOS technology. Due to the differential transmission technique and low voltage swing, LVDS(low-voltage differential signaling) has been widely used for high speed transmission with low power consumption. This interface circuit is fully compatible with the LVDS standard. The LVDS proposed in this paper utilizes a telescopic amplifier. This circuit is operated up to 2.3 Gbps. The circuit has a power consumption of 25. 5mW. This circuit is designed with Samsung $0.35{\mu}m$ CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.1
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• pp.1-7
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• 2007

In this paper, two kinds of initial oxidation methods i.e., SLTO(Slow Low Temperature Oxidation: $700^{\circ}C$) and RTO(Rapid Thermal Oxidation: $850^{\circ}C$) are applied prior to the plasma nitridation for ultra thin oxide of RPNO (Remote Plasma Nitrided Oxide). It is observed that SLTO has superior characteristics to RTO such as lower SS(Sub-threshold Slope) and improved Ion-Ioff characteristics. Low frequency noise characteristics of SLTO also showed better than RTO both in linear and saturation regime. It is shown that flicker noise is dominated by carrier number fluctuation in the channel region. Therefore, SLTO is promising for nano-scale CMOS technology with ultra thin gate oxide.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.1
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• pp.43-47
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• 2024

The size of semiconductor devices has been scaled down to improve packing density and output performance. However, there is uncontrollable spreading of the dopants that comprise the well, punch-stop, and channel-stop when using high-temperature annealing processes, such as rapid thermal annealing (RTA). In this context, low-temperature deuterium annealing (LTDA) performed at a low temperature of 300℃ is proposed to reduce the thermal budget during CMOS fabrication. The LTDA effectively eliminates the interface trap in the gate dielectric layer, thereby improving the electrical characteristics of devices, such as threshold voltage (V_TH), subthreshold swing (SS), on-state current (I_ON), and off-state current (I_OFF). Moreover, the LTDA is perfectly compatible with CMOS processes.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.309-315
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• 2010

A fully-differential low-voltage low-power electrocardiogram (ECG) amplifier by using the nonfeedback PMOS pseudo-resistors is proposed. It consists of two operational-transconductance amplifiers (OTA) in series (a preamplifier and a variable-gain amplifier). To make it insensitive to the gate leakage current of the OTA input transistor, the feedback pseudo-resistor of the conventional ECG amplifier is moved to input branch between the OP amp summing node and the DC reference voltage. Also, an OTA circuit with a Gm boosting block without reducing the output resistance (Ro) is proposed to maximize the OTA DC gain. The measurements shows the frequency bandwidth from 7 Hz to 480 Hz, the midband gain programmable from 48.7 dB to 59.5 dB, the total harmonic distortion (THD) less than 1.21% with a full voltage swing, and the power consumption of 233 nW in a 0.13 ${\mu}m$ CMOS process at the supply voltage of 0.7 V.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.1-6
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• 2011

Low-power logic gates, i.e. inverter, NAND, and NOR, are proposed employing only n-channel oxide thin film transistors (TFTs). The proposed circuits were designed to prevent the pull-up and pull-down switches from being turned on simultaneously by using asymmetric feed-through and bootstrapping, thereby exhibited same output voltage swing as the input signal and no static current. The inverter is composed of 5 TFTs and 2 capacitors. The NAND and the NOR gates consist of 10 TFTs and 4 capacitors respectively. The operations of the logic gates were confirmed successfully by SPICE simulation using oxide TFT model.

• Journal of the Semiconductor & Display Technology
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• v.16 no.1
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• pp.97-101
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• 2017

In this paper, IGZO thin film transistor (TFT) was fabricated with cross-linked Poly (4-vinylphenol) (PVP) gate dielectric for flexible, transparent display applications. The PVP is one of the candidates for low-temperature gate insulators. MIM structure was fabricated to measure the leakage current and evaluate the insulator properties according to the annealing temperature. Low leakage current ( <0.1nA/cm2 @ 1MV/cm ) was observed at $200^{\circ}C$ annealing condition and decreases much more as the annealing temperature increases. The electrical characteristics of IGZO TFT such as subthreshold swing, mobility and ON/OFF current ratio were also improved, which shows that the performance of IGZO TFTs with PVP can be enhanced by reducing the amount of incomplete crosslinking in PVP.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.276-281
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• 2005

This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.