• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.2
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• pp.47-54
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• 1986

Hardware implementation of a 32-channel MFC digital receiver has not been easy and simple, because it requires real time processing of PCM data. In this paper, we introduce a method of designing an MFC digital receiver compactly by the channel distribution method. We have implemented the MFC digital receiver to process many cnannels by distributing channels of the TDM input data directly to the commercial digital signal processor chips(NEC uPD7720), and by carrying out the modified Goertzel Algorithm. The design of low cost, reliable, high speed, and compact MFC receiver will be shown.

• Proceedings of the KIEE Conference
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• 2002.11c
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• pp.114-117
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• 2002

The airborne tracking radar is located in front of aircraft or missile and measures and tracks a target motion. The signal processor receives target signals from a receiver using A/D converters, and calculates the target motion, and transfers the data to the aircraft or missile control unit. Since the signal processing system is required to be lightweight and small size as well as high performance to calculate and analyze the received signal, we use high speed DSPs and SMD type components having low power consumption. In this paper, we describe the design concept of signal processing system of the airborne tracking radar.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.5
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• pp.61-70
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• 2004

The operation mode of neural network is divided into learning and recognition process. Learning is updating process of weight until neural network archives target result from input pattern. Recognition is arithmetic process of input pattern and weight. Traditional inner product process is focused to improve processing speed and hardware complexity. There is no hardware architecture to distinguish between loaming and recognition mode of neural network. In this paper we propose the new architecture of low power inner product processor for reconfigurable neural network. The proposed architecture is similar with bit-serial inner product processor on learning mode. It have several advantages which are fast processing base on bit-level, suitability of hardware implementation and pipeline architecture to compute data. And proposed architecture minimizes active units and reduces consumption power on recognition mode. Result of simulation shows that active units is depend on bit representation of weight, but we can reduce active units about 50 precent.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.941-944
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• 2003

This paper implement Telemetry System which is used Bluetooth. This System propose system which can detect a total amount of gas, electricity or water without a motorman, at home. BlueTooth is a close range wireless communication technology which uses a wireless frequency 2.4GHz and has a high trust and self - error correction technology according to a low power consumption quality and a high-speed frequency hopping. This makes get a high trust concerning a data transmission than an existing modem. In addition, though wireless modem is restricted by a minimal of a wireless terminal, it will be possible to coincide with the function of the portable with the low power consumption quality by using Bluetooth. And as the system on a chip of module progresses, the possibility of the snail size is present. And, Motorman who use mobility of embedded system can detect detect a total amount of gas, electricity or water outdoor. Embedded system use ARM processor that is low power processor. So it ran use long time efficiently.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.75-80
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• 1992

This paper deals with the design scheme of the custom control circuit for optimizing the interface of peripheral devices to general-purpose controllers for the high speed digital system. When the various peripheral devices such as memory, I/O devices and buffers which operate at low speed are interfaced to the microprocessor which operates at high speed, inserting the proper wait state to the processor is required. The proposed scheme designed with random logic may be applied to the high performance graphic system like the X-terminal. This circuit provides the flexibility and system independancy for the optimum digital system design.

• Proceedings of the KIEE Conference
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• 1997.07f
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• pp.2078-2081
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• 1997

IP speed controller is used as a main controller and it makes the system low overshoot and easy controllability. Load torque is estimated by Kalman filter algorithm and parameter controller is used against a rotor inertia negative variations. Parameter Controller (PC) is equipped with a torque observer implemented by software of a digital signal Processor. PC is a parameter controller which selects a moment of inertia J in responding to a load torque to control the system response.

• International Journal of Highway Engineering
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• v.15 no.6
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• pp.41-47
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• 2013

PURPOSES : The purpose of this study is about noise which is generated from roads and is consist of irregular frequency variation from low frequency to various band. The existing methods of noise reduction are sound barrier that uses insulation material and absorbing material or have applied passive technology of noise reduction by devices. The total frequency band is needed to apply active noise control. METHODS : In this study applies to the field of road traffic environment, signal processing controller and various analog signal input/output, the amplifier module is based on parallel-core embedded processor designed. DSP performs the control algorithm of the road traffic noise. Noise sources in the open space performance of evaluation were applied. In this study, controller of active signal processor was designed based on the module of audio input/output and main controller of embedded process. The controller of active signal processor operates noise reduction algorithm and performance tests of noise reduction in inside and outside environment were executed. RESULTS : The signal processing controller with OMAP-L137 parallel-core processors as the center, DSP processors in the active control operations dealt with quickly. To maximize the operation speed of an object and ARM processor is external function keys and display for functions and evaluating the performance management system was designed for the purpose of the interface. Therefore the reduction of road traffic noise has established an electronic controller-based noise reduction. CONCLUSIONS : It is shown that noise reduction is effective in the case of pour tonal sound and complex tonal sound below 500Hz by appling to Fx-LMS.

• The Journal of the Korea Contents Association
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• v.10 no.1
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• pp.103-113
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• 2010

The basic real-time scheduling algorithms based on RM or EDF approaches assume that the tasks are preemptive, but the tasks may contain nonpreemptive sections in many cases. Also the existing scheduling algorithm for reducing the power consumption of the processor is based on the task utilizations and determines the processor speed $S_H$ or $S_L$ according to the existence of the blocking intervals. In this algorithm, the $S_H$ interval that operates in high speed is the interval during which the priority inversion by blocking occurs, and the length of this interval is set to the task deadline that includes the blocking intervals. In this paper, we propose an improved algorithm that can reduce the power consumption ratio by shortening the length of the $S_H$ interval. The simulation shows that the power consumption ratio of the proposed algorithm is reduced as much as 13% compared to the existing one.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.2
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• pp.186-193
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• 2005

This paper presents a strategy to drive built in-type spindle induction motor which is used as CNC(Computer Numerical Control) in the industry. Gopinath model flux estimator which is composed of current model to be profitable in the low speed range and voltage model to be profitable in the high speed range is used for rotor flux estimation. Moreover this paper presents to drive the spindle motor in the high speed range by using the flux weakening control. High speed operation of spindle motor in the field weakening region is verified through simulations and experiments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.51-58
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• 2007

This paper presented an adaptive pipeline architecture for a high-performance and low-power asynchronous processor. The proposed pipeline architecture employed a stage-skipping and a stage-combining scheme. The stage-skipping scheme can skip the operation of a bubble stage that is not used pipeline stage in an instruction execution. In the stage-combining scheme, two consecutive stages can be joined to form one stage if the latter stage is empty. The proposed pipeline architecture could reduce the processing time and power consumption. The proposed architecture supports multi-processing in the EX stage that executes parallel 4 instructions. We designed an asynchronous microprocessor to estimate the efficiency of the proposed pipeline architecture that was synthesized to a gate level design using a $0.35-{\mu}m$ CMOS standard cell library. We evaluated the performance of the target processor using SPEC2000 benchmark programs. The proposed architecture showed about 2.3 times higher speed than the asynchronous counterpart, AMULET3i. As a result, the proposed pipeline schemes and architecture can be used for asynchronous high-speed processor design