• Proceedings of the KIPE Conference
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• 2006.06a
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• pp.485-487
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• 2006

Speed and torque controls of permanent magnet synchronous motors are usually attained by the application of position and speed sensors. However, speed and position sensors require the additional mounting space, reduce the reliability in harsh environments and increase the cost of a motor. Therefore, many studies have been performed for the elimination of speed and position sensors. This paper investigates an Improved sliding mode observer for the speed sensorless control of a permanent magnet synchronous motor. The proposed control strategy is the sliding mode observer with a variable boundary layer for a low-chattering and fast-reponse control. The proposed algorithm is verified through the simulation and experimentation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.11
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• pp.2281-2285
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• 2009

Powerline communication is the data signal which is modulated by carrier frequency through the installed powerline at in-home or office is transmitted and received signals are separated into data signal with using band-pass filter which cent-frequency is carrier frequency. The home gateway, an equipment which works as an gateway for ubiquitous home network, relays all functions of a home network. The home gateway must always be connected in order to provide seamless services. However it gives unfavorable power consumption. Therefore the needs for working in maximum power saving mode while there is no data traffic and for invoking to the normal function when it is necessary. So, in this paper we survey the development of low power PLC modem monitoring of power consumption and breaking abnormal power in the home Network.

• Journal of Power Electronics
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• v.10 no.1
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• pp.27-33
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• 2010

This paper presents a bidirectional DC-DC converter suitable for low-voltage super capacitor-based electric energy storage systems. The DC-DC converter presented here consists of a full-bridge circuit and a current-fed push-pull circuit with a high frequency (HF) transformer-link. In order to reduce the device-conduction losses due to the large current of the super capacitor as well as unnecessary ringing, synchronous rectification is employed in the super capacitor-charging mode. A wide range of voltage regulation between the battery and the super capacitor can be realized by employing a Phase-Shifting (PS) Pulse Width Modulation (PWM) scheme in the full-bridge circuit for the super capacitor charging mode as well as the overlapping PWM scheme of the gate signals to the active power devices in the push-pull circuit for the super capacitor discharging mode. Essential performance of the bidirectional DC-DC converter is demonstrated with simulation and experiment results, and the practical effectiveness of the DC-DC converter is discussed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.34-42
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• 2012

In this paper, a wide-input range CMOS multi-mode rectifier for wireless power transfer system is presented. The output voltage of multi-mode rectifier is sensed by comparator and switches are controlled based on it. The mode of multi-mode rectifier is automatically selected by the switches among full-wave rectifier, 1-stage voltage multiplier and 2-stage voltage multiplier. In full-wave rectifier mode, the rectified output DC voltage ranges from 9 V to 19 V for a input AC voltage from 10 V to 20 V. However, the input-range of the multi-mode rectifier is more improved than that of the conventional full-wave rectifier by 5V, so the rectified output DC voltage ranges from 7.5 V to 19 V for a input AC voltage from 5 V to 20 V. The power conversion efficiency of the multi-mode rectifier is 94 % in full-wave rectifier mode. The proposed multi-mode rectifier is fabricated in a $0.35{\mu}m$ CMOS process with an active area of $2500{\mu}m{\times}1750{\mu}m$.

• Journal of Periodontal and Implant Science
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• v.39 no.4
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• pp.385-390
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• 2009

Purpose: In this study we evaluated the morphologic aspects of defects created by a piezoelectric ultrasonic scaler with scaler tip on casting gold alloy using scanning electron microscope (SEM) images and defect surface profiles. Methods: 54 blocks of type III casting gold alloy (Firmilay, Jellenko Inc, CA, USA) were scaled by a piezoelectric ultrasonic scaler (P-MAX, Satelec, France) with scaler tip (No. 1 tip) on a sledge device. 2-dimensional profiles of defects on all samples were investigated by a surface profilometer (a-Step 500, KLA-Tencor, CA, USA). The selected working parameters were lateral force (0.5 N, 1.0 N, 2.0 N), mode (P mode, S mode), and power setting (2, 4, 8). SEM images were obtained. Defect surface profiles were made on Microsoft Excel program using data obtained by a surface profilometer. Results: Among P mode samples, there were similarities on defect surface profiles and SEM images regardless of lateral force. The defects created in P mode were narrow and shallow although the depth and the width increased as power setting changed low (2) to high (8). In P mode samples, the defect depth was the greatest when lateral force of 0.5 N was applied. However all the depths were smaller than 1 m. SEM images of Lateral force of 0.5 N, S mode, power setting 2 and 4 were similar to that of P mode, but the other SEM images of S mode showed discernible changes. Defect depth of S mode samples was the greatest when lateral force of 1.0 N was applied. Conclusions: Within the limitations of this study, it can be concoluded that removing capability of piezoelectric scaler with scaler tip becomes maximized as power level becomes higher but the capability is restricted when excessive lateral force is applied on scaler tip.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.4
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• pp.593-600
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• 2016

The solar array regulator for low earth orbit satellites controls a operating point of solar array for suppling electric power to the battery and the other units. Because the control object is reversed, the new approach for large and small signal analysis is needed despite using buck-converter for power stage. In this paper, the steady state analysis of solar array regulator is performed in continuous conduction mode and discontinuous conduction mode, and the border condition for each mode is established. Also, the small signal model of solar array regulator is established in discontinuous conduction mode. Experiments are carried on in worst condition which the solar array regulator can face with discontinuous conduction mode. The results show that the solar array regulator is in stable.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.45-49
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• 2009

In this paper, a direct down conversion LNA/Mixer has been designed and tested for 900Mhz UHF RFID application. The designed circuit has been implemented in 0.18um CMOS technology with 3.3V operation. In this work, a common gate input architecture has been used to cope with the higher input self jamming level. This LNA/Mixer is designed to support two operating modes of high gain mode and low gain mode according to the input jamming levels. The measured results show that the input referred P1dBs are 4dBm of high gain mode and 11dBm of low gain mode, and the conversion gains are 12dB and 3dB in high and low gain mode respectively The power consumptions are 60mW for high gain mode and 79mW for low gain mode. The noise figures are 16dB and 20dB in high gain mode and low gain mode respectively.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.37-43
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• 1997

In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

• Journal of Power Electronics
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• v.15 no.4
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• pp.1026-1034
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• 2015

In this paper, a unified control strategy using the current space vector modulation (CSVM) technique is proposed and applied to a bidirectional three-phase DC/AC converter. The operation of the converter changes with the direction of the power flow. In the charging mode, it works as a buck type rectifier; and during the discharging mode, it operates as a boost type inverter, which makes it suitable as an interface between high voltage AC grids and low voltage energy storage devices. This topology has the following advantages: high conversion efficiency, high power factor at the grid side, tight control of the charging current and fast transition between the charging and discharging modes. The operating principle of the mode analysis, the gate signal generation, the general control strategy and the transition from a constant current (CC) to a constant voltage (CV) in the charging mode are discussed. The proposed control strategy has been validated by simulations and experimental results obtained with a 1kW laboratory prototype using supercapacitors as an energy storage device.