• 전기전자학회논문지
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• 제11권2호
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• pp.83-88
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• 2007

이 논문은 MOS 전류모드 논리 (MOS current-mode logic circuit, MCML) 회로를 이용하여 저 전력 특성을 갖는 8${\times}$8 비트 병렬 곱셈기를 설계하였다. 이 8${\times}$8 병렬 곱셈기는 제안한 MCML 구조의 전가산기와 기존의 전가산기를 이용하여 설계하였다. 설계한 곱셈기는 기존 곱셈기에 비해 전력소모에서 9.4% 감소하였으며, 전력소모와 지연시간의 곱에서 11.7%의 성능향상이 있었다. 이 회로는 삼성 0.35${\mu}m$ 표준 CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.

• 동력기계공학회지
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• 제18권5호
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• pp.129-136
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• 2014

This paper proposes improvement on sensorless vector control performance of a permanent magnet synchronous motor (PMSM) with sliding mode observer. An adaptive observer gain and second order cascade low-pass filter (LPF) were used to improve the estimation accuracy of the rotor position and speed. The adaptive observer gain was applied to suppress the chattering intensity and obtained by using the Lyapunov's stability criterion. The second order cascade LPF was designed for the system to escalate the filtering performance of the back-emf estimation. Furthermore, genetic algorithm was used to optimize the system PI controller's performance. Simulation results showed the effectiveness of the suggested improvement strategy. Moreover, the strategy was useful for the sensorless vector control of PMSM to operate on the low-speed area.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.433-434
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• 2007

This paper describes a low-voltage dynamic random-access memory (DRAM) focusing on subthreshold leakage reduction during self-refresh (sleep) mode. By sharing a power switch, multiple iterative circuits such as row and column decoders have a significantly reduced subthreshold leakage current. To reduce the leakage current of complex logic gates, dual channel length scheme and input vector control method are used. Because all node voltages during the standby mode are deterministic, zigzag super-cutoff CMOS is used, allowing to Preserve internal data. MTCMOS technique Is also used in the circuits having no need to preserve internal data. Sub-1.2-V 1-Gb mobile DDR DRAM employing all these low-power techniques was designed in a 60 nm CMOS technology and achieved over 77% reduction of overall leakage current during the self-refresh mode.

• 전력전자학회논문지
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• 제4권1호
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• pp.91-98
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• 1999

본 논문에서는 역률개선용 단일 스위치 부스트 플라이백 결합형 ZCS quasi-resonant converter(QRC)를 제안한다. 제안된 컨버터는 입력전류를 불연속 모드로 동작시켜 역률을 개선하며 입력전류의 zero-crossing-point에서의 왜곡을 개선함으로써 고조파를 감소시켜 역률을 향상시켰으며 좋은 출력전압의 regulation 성능을 가지고 있다. 그리고 체계적인 설계를 위하여 설계식을 제안하였으며 제안된 설계식을 통하여 프로토타입 컨버터를 설계하였다. 실험결과 효율은 약 86%, 역률은 약 0.985이상을 얻었다. 따라서 본 컨버터는 스위칭 주파수가 수백 kHz이상이고 높은 regulation성능을 요구하는 낮은 전압의 소용량 컨버터에 적합하다.

• Journal of Power Electronics
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• 제15권6호
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• pp.1609-1618
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• 2015

DC microgrids are considered as prospective systems because of their easy connection of distributed energy resources (DERs) and electric vehicles (EVs), reduction of conversion loss between dc output sources and loads, lack of reactive power issues, etc. These features make them very suitable for future industrial and commercial buildings' power systems. In addition, the bipolar-type dc system structure is more popular, because it provides two voltage levels for different power converters and loads. To keep voltage balanced in such a dc system, a bidirectional dual buck-boost voltage balancer with direct coupling is introduced based on P-cell and N-cell concepts. This results in greatly enhanced system reliability thanks to no shoot-through problems and lower switching losses with the help of power MOSFETs. In order to increase system efficiency and reliability, a novel burst-mode control strategy is proposed for the dual buck-boost voltage balancer. The basic operating principle, the current relations, and a small-signal model of the voltage balancer are analyzed under the burst-mode control scheme in detail. Finally, simulation experiments are performed and a laboratory unit with a 5kW unbalanced ability is constructed to verify the viability of the bidirectional dual buck-boost voltage balancer under the proposed burst-mode control scheme in low-voltage bipolar-type dc microgrids.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.802-809
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• 2014

This paper presents a dual-mode bias modulator (BM) for complementary metal oxide semiconductor (CMOS) power amplifiers (PAs). The BM includes a hybrid buck converter and a normal buck converter for an envelope tracking (ET) mode for high output power and for an average power tracking (APT) mode for low output power, respectively. The dual-mode BM and CMOS PA are designed using a $0.18-{\mu}m$ CMOS process for the 1.75 GHz band. For the 16-QAM LTE signal with a peak-to-average power ratio of 7.3 dB and a bandwidth of 5 MHz, the PA with the ET mode exhibited a poweradded efficiency (PAE) of 39.2%, an EVM of 4.8%, a gain of 19.0 dB, and an adjacent channel leakage power ratio of -30 dBc at an average output power of 22 dBm, while the stand-alone PA has a PAE of 8% lower at the same condition. The PA with APT mode has a PAE of 21.3%, which is an improvement of 13.4% from that of the stand-alone PA at an output power of 13 dBm.

• International Journal of Aeronautical and Space Sciences
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• 제17권4호
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• pp.631-640
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• 2016

A dual-mode power management for a hybrid-electric UAV with a cruise power of 200W is proposed and empirically verified. The subject vehicle is a low-speed long-endurance UAV powered by a solar cell, a fuel cell, and a battery pack, which operate in the same voltage bounds. These power sources of different operational characteristics can be managed in two different methods: passive management and active management. This study proposes a new power management system named PMS2, which employs a bypass circuit to control the individual power sources. The PMS2 normally operates in active mode, and the bypass circuit converts the system into passive mode when necessary. The output characteristics of the hybrid system with the PMS2 are investigated under simulated failures in the power sources and the conversion of the power management methods. The investigation also provides quantitative comparisons of efficiencies of the system under the two distinct power management modes. In the case of the solar cell, the efficiency difference between the active and the passive management is shown to be 0.34% when the SOC of the battery is between 25-65%. However, if the SOC is out of this given range, i.e. when the SOC is at 90%, using active management displays an improved efficiency of 6.9%. In the case of the fuel cell, the efficiency of 55% is shown for both active and passive managements, indicating negligible differences.

• Journal of Power Electronics
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• 제16권5호
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• pp.1813-1820
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• 2016

Dual-mode photovoltaic power system should be capable of operating in grid-connected (GC) and stand-alone (SA) modes for distributed generation. Under different working modes, the optimal parameters of inverter output filters vary. Inverters commonly operate in GC mode, and thus, a small capacitance is beneficial to the GC topology for achieving a reasonable compromise. A predictive current control scheme is proposed to control the grid current in GC mode and thereby obtain high-performance power. As filter are not optimal under SA mode, a compound control strategy consisting of predictive current control, instantaneous voltage control, and repetitive control is proposed to achieve low total harmonic distortion and improve the output voltage spectrum. The seamless transfer between GC mode and SA mode is illustrated in detail. Finally, the simulation and experimental results of a 4 kVA prototype demonstrate the effectiveness of the proposed control strategy.

• 전자공학회논문지
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• 제51권4호
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• pp.49-58
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• 2014

본 논문에서는 저전력 고속 모바일 I/O 인터페이스를 위한 저스윙 차동 니어-그라운드 시그널링 (NGS) 트랜시버를 소개한다. 제안하는 트랜스미터는 온-칩 레귤레이터로 정류된 프로그래머블한 스윙을 가지는 전압-모드 드라이버와 비대칭 상승/하강시간을 가지는 전단드라이버를 사용한다. 제안하는 리시버는 고주파이득을 신장시키는 피드-포워드 커패시터를 이용한 새로운 다중경로이득 차동앰프를 사용한다. 또한, 이 리시버는 가변적인 트랜스미터 출력스윙에 의한 입력 공통모드 변화를 보상하며, 리시버 입력단 증폭기의 전류 미스매치를 최소화하기 위하여 새로운 적응형 바이어스 생성기를 포함한다. 트랜스미터와 리시버에 적용된 새로운 간단하고 효과적인 임피던스 매칭 기술들의 사용으로 우수한 시그널 인테그리티와 높은 파워 효율을 이뤄냈다. 65 nm CMOS 공정으로 설계된 제안하는 트랜시버는 10 cm 길이의 FR4 PCB에서 채널당 13 Gbps의 전송속도와 0.3 pJ/bit (= 0.3 mW/Gbps)의 높은 파워 효율을 갖는다.

• 전력전자학회논문지
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• 제24권3호
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• pp.207-214
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• 2019

In this study, discrete-time domain analysis is proposed to investigate the input current of a buck AC/DC light-emitting diode (LED) driver. The buck power factor correction converter can operate in both discontinuous conduction mode (DCM) and continuous conduction mode (CCM). Two discontinuous and two continuous conduction operating modes are possible depending on which event terminates the conduction of the main switch in a switching cycle. All four operating modes are considered in the discrete-time domain analysis. The peak current-mode control with slope compensation is used to design a low-cost AC/DC LED driver. A slope compensation design of the buck AC/DC LED driver is described on the basis of a discrete-time domain analysis. Experimental results are presented to confirm the usefulness of the proposed analysis.