• Journal of Electrical Engineering and Technology
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• 제13권5호
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• pp.1807-1813
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• 2018

In this paper, the fault line selection and location problems of single line-to-ground (SLG) fault in distribution network are addressed. Firstly, the adaptive filtering property for empirical mode decomposition is formulated. Then in view of the different characteristics showed by the intrinsic mode functions(IMF) under different fault inception angles obtained by empirical mode decomposition, the sign of peak value about the low-frequency IMF and the capacitance transient energy is chosen as the fault line selection criteria according to the different proportion occupied by the low-frequency components. Finally, the fault location is determined based upon the comparison result with adjacent fault passage indicators' (FPI) waveform on the strength of the interaction between the distribution terminal unit(DTU) and the FPI. Moreover, the logic nodes regarding to fault line selection and location are newly expanded according to IEC61850, which also provides reference to acquaint the DTU or FPI's function and monitoring. The simulation results validate the effectiveness of the proposed fault line selection and location methods.

• 전자공학회논문지CI
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• 제47권1호
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• pp.30-40
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• 2010

IPTV 셋톱박스에서 가장 많이 사용하는 저장장치인 하드디스크는 가격에 비해 저장용량이 크고 입출력 속도가 빠르지만 스핀들 모터의 기계적 동작으로 인해 전력 소모가 많다는 단점이 있다. 셋톱박스에서 스트리밍 데이터를 재생하기 위하여 하드디스크의 스핀들 모터는 최대 전력을 사용하는 활성모드를 계속 유지해야 한다. 본 논문에서는 스트리밍 데이터 재생 시 전력 소모를 감소시키는 오프셋-버퍼링(Offset-Buffering)과 다중모드 스핀-다운(Multi Mode Spin-Down) 기법을 제안한다. 오프셋-버퍼링은 사용자의 시청 패턴을 분석하고 분석된 결과를 통해 버퍼링을 하므로 스핀들 모터의 모드를 대기모드로 길게 유지할 수 있다. 또한 오프셋 버퍼의 크기에 따라 다양한 모드로 스핀-다운을 하여 전력 소모를 줄일 수 있다. 실험 결과 본 논문에서 제안한 오프셋-버퍼링과 다중모드 스핀-다운은 기존의 풀-버퍼링(Full-Buffering)보다 28.3% 전력 소모량을 감소시켰으며, 스핀-업 횟수를 12.5% 줄였다.

• 한국전자통신학회논문지
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• 제14권6호
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• pp.1145-1152
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• 2019

본 논문에서는 디지털 회로와 저소비전력 및 고속연산의 장점을 가진 아날로그 회로를 혼용하기 위하여, 저전력 전류모드 12비트 ADC(: Analog to Digital Converter)를 제안하였다. 제안하는 12비트 ADC는 4비트 ADC의 cascade 구조를 사용하여 소비전력을 줄일 수 있었으며, 변환 current mirror 회로를 사용해 칩면적을 줄일 수 있었다. 제안된 ADC는 매그나칩/SK하이닉스 350nm 공정으로 구현하였고, Cadence MMSIM을 사용하여 post-layout simulation를 진행하였다. 전원전압 3.3V에서 동작하고, 면적은 318㎛ x 514㎛를 차지하였다. 또한 제안하는 ADC는 평균 소비전력 3.4mW의 저소비전력으로 동작하는 가능성을 나타내었다.

• 대한전기학회논문지
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• 제41권8호
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• pp.841-849
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• 1992

In power system operation, the stability of synchronous machine has been recognized one of the most important things. AESOPS program developed by EPRI in U.S.A. is a frequency domain analysis program in power system stability and it computes the electro-mechanical oscillation mode. This paper presents how to analyze the power system small signal stability problem efficiently by uusing the AESOPS program and analyze the various factors affecting the damping characteristics of these oscillations in KEPCO power system of 1986 with pumped-storage plant. To reduce the computing time and efforts, selecting the poorly-damped oscillation mode and clustering technique have been used. The characteristics of load, the amount of power flow on the transmission line and the gain of exciter have a significant effects on the damping of the system while the governing system has only a minor one. With the Power System Stabilizers, the stability of the power system has been improved.

• 전기학회논문지P
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• 제57권3호
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• pp.255-259
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• 2008

In this paper, a current-mode integrator for low-voltage, low-power analog integrated circuits is presented. Using the proposed current-mode integrator, the baseband analog filter is designed for WCDMA wireless communication. To verify the proposed current-mode integrator circuit, Hspice simulation using 1.8V TSMC $0.18{\mu}m$ CMOS parameter is performed and achieved 44.9dB gain, 15.7MHz unity gain frequency. The described 3rd-order current-mode baseband analog filter is composed of the proposed current-mode integrator, and SFG(Signal Flow Graph) method is used to realize the baseband filter. The simulated results show 2.12MHz cutoff frequency which is suitable for WCDMA baseband block.

• 한국산업정보학회논문지
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• 제18권5호
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• pp.25-32
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• 2013

고속 저전력 모바일 응용분야를 위한 1.8V 2-Gb/s scalable low voltage signaling (SLVS) 송신단을 제안한다. 제안하는 송신단은 데이터 전송을 위한 4-lane 송신단, 소스 동기 클록 방식을 위한 1-lane 송신단, 그리고 8-phase 클록 발생기로 구성된다. 제안하는 SLVS 송신단은 50 mV에서 650 mV의 출력 전압 범위를 가지며 고속 동작 모드와 저전력 모드를 제공한다. 또한, signal integrity를 개선하기 위한 출력 드라이버의 임피던스 교정 기법이 제안된다. 제안하는 SLVS 송신단은 1.8 V의 공급 전압을 가지는 0.18-${\mu}m$ 1-poly 6-metal CMOS 공정을 이용하여 구현된다. 구현된 SLVS 송신단의 데이터 jitter의 시뮬레이션 결과는 2-Gb/s의 데이터 전송속도에서 8.04 ps이다. 1-lane을 위한 SLVS 송신단의 면적과 전력소모는 각각 $422{\times}474{\mu}m^2$와 5.35 mW/Gb/s이다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2015년도 제46회 하계학술대회
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• pp.1060-1061
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• 2015

This paper presents the control method of MPPT (Maximum Power Point Tracking) using back-to- back converter. The windturbine system use PMSG(ermanent Magnet Synchronous Generator) system considering low maintenance costs and driving performance at low wind. This paper use the adaptive sliding mode control to the torque control. Proposed method was analyzed mathematically.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• Journal of Advanced Marine Engineering and Technology
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• 제26권6호
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• pp.631-637
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• 2002

Two stroke low speed diesel engines are used as a power supplier not only for marine vessel but also diesel power plant with a benefit of its higher mobility and durability than the other thermal engines. However, there are some disadvantages such as the bigger vibrating excitation forces generated by high combustion pressure in cylinders which various kinds of vibrations are caused. In this paper, it is theoretically studied to control engine body vibration using dynamic vibration absorber. As an actual case, dynamic absorbers are designed for controlling X-mode vibration of 9K80MC-S engine on the diesel power plant and its performance is identified by the vibration test both in shop and site

• 전력전자학회논문지
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• 제18권4호
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• pp.387-396
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• 2013

This paper investigates the droop control of parallel inverters for an islanded mode of microgrid. Frequency and voltage droop control is one of power control and load demand sharing methods. However, although the active power is properly shared, the reactive power sharing is inaccurate with conventional method due to the unequal line impedances and the power coupling of active - reactive power. In order to solve this problem, an improved droop method with virtual inductor concept and a voltage and current controller properly designed have been considered and analyzed through the PSiM simulation. The performance of improved droop method is analyzed in not only low-voltage line but also medium voltage line.