• Journal of Power Electronics
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• 제4권4호
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• pp.237-245
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• 2004

In this paper, a two-switch high frequency flyback transformer linked zero voltage soft switching PWM DC-DC power converter implemented for distributed DC- feeding power conditioning supplies is proposed and discussed. This switch mode power converter circuit is mainly based on two main active power semiconductor switches and a main flyback high frequency transformer linked DC-DC converter in which, two passive lossless quasi-resonant snubbers with pulse current regeneration loops for energy recovery to the DC supply voltages composed of a three winding auxiliary high frequency pulse transformer, auxiliary capacitors and auxiliary diodes for inductive energy recovery discharge blocking due to snubber capacitors are introduced to achieve zero voltage soft switching from light to full load conditions. It is clarified that the passive resonant snubber-assisted soft switching PWM DC-DC power converter has some advantages such as simple circuit configuration, low cost, simple control scheme, high efficiency and lowered noises due to the soft switching commutation. Its operating principle is also described using each mode equivalent circuit. To determine the optimum resonant snubber circuit parameters, some practical design considerations are discussed and evaluated in this paper. Moreover, through experimentation the practical effectiveness of the proposed soft switching PWM DC-DC power converter using IGBTs is evaluated and compared with a hard switching PWM DC-DC power converter.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2007년도 춘계종합학술대회
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• pp.528-531
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• 2007

본 논문에서는 4인치 WVGA 광학 보상 복굴절형 (Optical Compensated Bend, OCB) 디스플레이 패널을 제안한다. 개발한 패널은 블랙 데이터 삽입 기능을 가진 저온 폴리 실리콘 (low-temperature poly-Si, LTPS) 집적 게이트 구동 회로를 내장하고 있다. 블랙 데이터 삽입 기능은 4ms의 고속 응답 시간 및 $160^{\circ}$의 광 시야각을 가능하게 한다. 본 연구에서는 상대적으로 적은 소비전력을 가진 밝은 영상에 대해 RGBW 픽 셀 구조를 적용하였다. 패널의 특성은 OCB 광학효율을 극대화하였고, 구동 중 영상의 안정성을 유지하는 목표를 달성 할 수 있었다. 패널 상에 OCB 구동을 위해 필요한 회로를 LTPS를 이용하여 설계함으로써 새로운 외부 구동 IC 개발 없이 고효율 OCB 모드를 구현할 수 있었다.

• Transactions on Electrical and Electronic Materials
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• 제14권5호
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• pp.235-241
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• 2013

A low power CMOS control circuit is applied in an integrated DC-DC buck converter. The integrated converter is composed of a feedback control circuit and power block with 0.35 ${\mu}m$ CMOS process. A current-sensing circuit is integrated with the sense-FET method in the control circuit. In the current-sensing circuit, a current-mirror is used for a voltage follower in order to reduce power consumption with a smaller chip-size. The N-channel MOS acts as a switching device in the current-sensing circuit where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time. The converter offers well-controlled output and accurately sensed inductor current. Simulation work shows that the current-sensing circuit is operated with an accuracy of higher than 90% and the transient time of the error amplifier is controlled within $75{\mu}sec$. The sensing current is in the range of a few hundred ${\mu}A$ at a frequency of 0.6~2 MHz and an input voltage of 3~5 V. The output voltage is obtained as expected with the ripple ratio within 1%.

• 전기학회논문지
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• 제58권7호
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• pp.1255-1262
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• 2009

The present study explained the phenomenon that low frequency oscillation is synchronized with discrete data obtained from a wide area system, and a sync search method. When a disturbance occurs in an power system, various controllers operate in order to maintain synchronization. If the system's damping is poor, low frequency oscillations continue for a long time and the oscillations are synchronized with one another at specific frequency. The present study estimated dominant modes, magnitude and phase of signals by applying parameter estimation methods to discrete signals obtained from an power system, and performed sync search among wide area signals by comparing the estimated data. Sync search was performed by selecting those with the same frequency and damping constant from dominant oscillation modes included in a large number of signals, and comparing their magnitude and phase. In addition, we defined sync indexes in order to indicate the degree of sync between areas in a wide area system. Furthermore, we proposed a wide area sync search method by normalizing mode magnitude in discrete data obtained from critical generator of the wide area. By applying the sync search method and sync indexes proposed in this study to two area systems, we demonstrated that sync scanning can be performed for discrete signals obtained from power systems.

• Journal of Electrical Engineering and Technology
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• 제10권5호
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• pp.2031-2039
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• 2015

In the LED lighting industry, the dimming function in the LED lamp is required by demands of many consumers. To drive this LED lighting, various types of power converters have been applied. Among them, an LLC resonant converter could be applied for high power LED lighting because of its high efficiency and high power density, etc. The function of power factor correction (PFC) might be added to it. In this paper, a dimmable single-stage asymmetrical LLC resonant converter is proposed. The proposed converter performs both input-current harmonics reduction and PFC using the discontinuous conduction mode (DCM). Also, the lower voltage stress across switching devices as well as the zero voltage switching (ZVS) in switching devices is realized by the proposed topology. It can reduce cost and has high efficiency of the driver. In addition, the regulation of the output power by variable switching frequency can vary the brightness of a light. In the proposed converter, one of the attractive advantages doesn’t need any extra control circuits for the dimming function. To verify the performance of the proposed converter, simulation and experimental results from a 300W prototype are provided.

• Journal of Electrical Engineering and Technology
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• 제8권1호
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• pp.137-143
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• 2013

This paper presents development of variable speed generation (VSG) system with energy saving function. The rubber tyred gantry crane (RTGC) requires the power from diesel-engine. Significant fuel savings by reducing the engine speed can be achieved, because all of operation modes except hoisting are required lower power than rated value of engine. When low speed operation output voltage of generator is decrease until acceptable range of motor driver inverters and auxiliary load supplier. According to power demand engine speed is varying from 20 to 60Hz, and voltage is varying between 210Vac and 480Vac. When idle mode or low power operation dc/dc converter operates by constant output voltage control and inverters dc site voltage is compensated by it. This paper proposed 3-phase interleaved boost converter which has the same structure as the commercially available 3-phase inverter and current sharing capability. 400kW interleaved converter is designed and a performance of converter is evaluated through several experiments with a RTGC system. Energy saving VSG system can cut down fuel consumption by 36% and 21.3% at idle and unidirectional load operations.

• Journal of Power Electronics
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• 제9권2호
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• pp.133-145
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• 2009

In this paper a modular high performance MV-to-LV rectifier based on a cascaded H-bridge rectifier is presented. The proposed rectifier can directly connect to the medium voltage levels and provide a low-voltage and highly-stable DC interface with the consumer applications. The input stage eliminates the necessity for heavy and bulky step-down transformers. It corrects the input power factor and maintains the voltage balance among the individual DC buses. The second stage includes the high frequency parallel-output DC/DC converters which prepares the galvanic isolation, regulates the output voltage, and attenuates the low frequency voltage ripple ($2f_{line}$) generated by the first stage. The parallel-output converters can work in interleaving mode and the active load-current sharing technique is utilized to balance the load power among them. The detailed analysis for modeling and control of the proposed structure is presented. The validity and performance of the proposed topology is verified by simulation and experimental results.

• Nuclear Engineering and Technology
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• 제44권5호
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• pp.459-470
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• 2012

From the PSA point of view, the Fukushima accident of Japan in 2011 reveals some issues to be re-considered and/or improved in the PSA such as the limited scope of the PSA, site risk, etc. KAERI (Korea Atomic Energy Research Institute) has performed researches on the development of an integrated risk assessment framework related to some issues arisen after the Fukushima accident. This framework can cover the internal PSA model and external PSA models (fire, flooding, and seismic PSA models) in the full power and the low power-shutdown modes. This framework also integrates level 1, 2 and 3 PSA to quantify the risk of nuclear facilities more efficiently and consistently. We expect that this framework will be helpful to resolve the issue regarding the limited scope of PSA and to reduce some inconsistencies that might exist between (1) the internal and external PSA, and (2) full power mode PSA and low power-shutdown PSA models. In addition, KAERI is starting researches related to the extreme external events, the risk assessment of spent fuel pool, and the site risk. These emerging issues will be incorporated into the integrated risk assessment framework. In this paper the integrated risk assessment framework and the research activities on the emerging issues are outlined.

• 한국정보통신학회논문지
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• 제15권4호
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• pp.913-920
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• 2011

본 논문에서는 수동형 900MHz RFID 태그 칩용 로직 공정 기반 저면적.저전력 1Kb EEPROM를 설계하였다. 1Kb 셀 배열 (cell array)은 1 워드 (word)의 EEPROM 팬텀 셀 (phantom cell)을 2차원 배열 형태인 (16행 ${\times}$ 16열) ${\times}$ 4블록으로 구성하였으며, 4개의 메모리 블록이 CG (Control Gate)와 TG (Tunnel Gate) 구동회로를 공유하므로 저면적 IP 설계를 하였다. TG 구동회로를 공유하기 위해 소자간의 전압을 신뢰성이 보장되는 5.5V 이내로 유지하면서 동작 모드별 TG 바이어스 전압을 스위칭해 주는 TG 스위치 회로를 제안하였다. 그리고 4 메모리 블록 중 하나의 블록만 활성화하는 partial activation 방식을 사용하므로 읽기 모드에서 전력소모를 줄였다. 그리고 하나의 열 (column)당 연결되는 셀의 수를 줄이므로 읽기 모드에서 BL (Bit-Line)의 스위칭 시간을 빠르게 하여 액세스 시간 (access time)을 줄였다. Tower $0.18{\mu}m$ CMOS 공정을 이용하여 (32행 ${\times}$ 16열) ${\times}$ 2블록과 (16행 ${\times}$ 16열) ${\times}$ 4블록의 2가지 배열 형태의 1Kb EEPROM IP를 설계하였으며, (16행 ${\times}$ 16열) ${\times}$ 4블록의 IP가 (32행 ${\times}$ 16열) ${\times}$ 2블록의 IP에 비해 레이아웃 면적은 11.9% 줄였으며, 읽기 모드 시 전력소모는 51% 줄였다.

• 전자공학회논문지SC
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• 제38권2호
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• pp.31-37
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• 2001

광디스크 재생기에서 사용되는 디지털 서보는 주변 블록과의 집적화가 유리하고, 온도변화에 따른 열화가 적으며, 각종 픽업에 대한 유연한 대응이 가능한 장점 때문에 이용도가 점점 높아지고 있는 추세이다.[6] 그러나 디지털 시그널 프로세서를 내장한 디지털 서보는 전력 소비량이 매우 큰 단점을 가지고 있다. 본 논문에서는 광디스크 재생기의 특성 상 초기화 시간에 대부분의 기능이 몰려 있으므로 DSP의 사이클 수는 많이 차지 하나, 실제로 전력 소비에 주된 영향을 끼치는 시간은 초기화 시간이 아닌 재생 모드 시간 임에 착안하여 디지털 서보의 소비 전류를 획기적으로 줄일 수 있는 방안을 제시하였다. 재생 모드에서의 필터 처리 사이클 수를 최대한 줄일 수 있도록 아키텍쳐를 변환함과 동시에 디지털 서보의 재생 모드를 병렬 처리함으로써, 전체 시스템의 소비 전력을 크게 줄이는 효과를 얻을 수 있도록 하였다. 즉, 광디스크 재생기의 디지털 서보에 포함되는 DSP 코아의 리소스 공유를 통해DSP의 동작 속도와 부하를 크게 줄임으로써 소비 전류를 획기적으로 줄이는 효과를 얻어낸 것이다. 이러한 개념은 DSP-코아 뿐만 아니라, ROM, RAM에도 모두 적용되어 기존 아키텍쳐의 디지털 서보에 비해 소비 전류를 83% 가까이 줄일 수 있는 효과를 얻을 수 있었다.