• 전력전자학회:학술대회논문집
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• 전력전자학회 2006년도 전력전자학술대회 논문집
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• pp.485-487
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• 2006

Speed and torque controls of permanent magnet synchronous motors are usually attained by the application of position and speed sensors. However, speed and position sensors require the additional mounting space, reduce the reliability in harsh environments and increase the cost of a motor. Therefore, many studies have been performed for the elimination of speed and position sensors. This paper investigates an Improved sliding mode observer for the speed sensorless control of a permanent magnet synchronous motor. The proposed control strategy is the sliding mode observer with a variable boundary layer for a low-chattering and fast-reponse control. The proposed algorithm is verified through the simulation and experimentation.

• 전기학회논문지
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• 제58권11호
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• pp.2281-2285
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• 2009

Powerline communication is the data signal which is modulated by carrier frequency through the installed powerline at in-home or office is transmitted and received signals are separated into data signal with using band-pass filter which cent-frequency is carrier frequency. The home gateway, an equipment which works as an gateway for ubiquitous home network, relays all functions of a home network. The home gateway must always be connected in order to provide seamless services. However it gives unfavorable power consumption. Therefore the needs for working in maximum power saving mode while there is no data traffic and for invoking to the normal function when it is necessary. So, in this paper we survey the development of low power PLC modem monitoring of power consumption and breaking abnormal power in the home Network.

• Journal of Power Electronics
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• 제10권1호
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• pp.27-33
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• 2010

This paper presents a bidirectional DC-DC converter suitable for low-voltage super capacitor-based electric energy storage systems. The DC-DC converter presented here consists of a full-bridge circuit and a current-fed push-pull circuit with a high frequency (HF) transformer-link. In order to reduce the device-conduction losses due to the large current of the super capacitor as well as unnecessary ringing, synchronous rectification is employed in the super capacitor-charging mode. A wide range of voltage regulation between the battery and the super capacitor can be realized by employing a Phase-Shifting (PS) Pulse Width Modulation (PWM) scheme in the full-bridge circuit for the super capacitor charging mode as well as the overlapping PWM scheme of the gate signals to the active power devices in the push-pull circuit for the super capacitor discharging mode. Essential performance of the bidirectional DC-DC converter is demonstrated with simulation and experiment results, and the practical effectiveness of the DC-DC converter is discussed.

• 대한전자공학회논문지SD
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• 제42권11호
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• pp.9-16
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• 2005

이 논문에서는 다중 동작 주파수를 갖는 고성능 저전력 SoC에 사용 가능한 광대역 입출력 주파수를 지원하는 프로그램머블 PLL 기반의 클록킹 회로을 제안하였다. 제안된 클록 시스템은 이중 전하펌프를 이용 locking 시간을 감소시켰고, 광대역 주파영역에서 동작이 가능하도록 하였다. 칩의 저 전력 동작을 위해 동작 대기모드 시에 불필요한 PLL 회로를 지속적으로 동작시키지 않고 relocking 정보를 DAC를 통해 보존하고 불필요한 동작을 억제하였고, 대기모드에서 빠져나온 후 tracking ADC(Analog to Digital Converter)를 이용하여 빠른 relocking이 가능하도록 설계하였다. 또한 프로그램머블하게 출력 주파수를 선택하게 하는 구조를 선택하여 저 전력으로 최적화된 동작 주파수를 지원하기 위한 DFS(Dynamic frequency scaling) 동작이 가능하도록 클록 시스템을 설계하였다. 제안된 PLL 기반의 클록 시스템은 $0.35{\mu}m$ CMOS 공정으로 구현하였으며 2.3V의 공급전압에서 $0.85{\mu}sec\~1.3{\mu}sec$($24\~26$사이클)의 relocking 시간을 가지며, 파워다운 모드 적용 시 PLL의 파워소모는 라킹 모드에 비해 $95\%$이상 절감된다. 또한 제안된 PLL은 프로그래머블 주파수 분주기를 이용하여 다중 IP 시스템에서의 다양한 클록 도메인을 위해 $81MHz\~556MHz$의 넓은 동작 주파수를 갖는다.

• 대한전자공학회논문지SD
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• 제49권4호
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• pp.34-42
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• 2012

본 논문에서는 무선전력전송 시스템 수신부의 넓은 입력 범위의 CMOS 다중 모드 정류기를 설계하였다. 다중 모드 정류기의 출력전압을 비교기로 감지하고, 스위치를 컨트롤 하여 정류기 모드를 전환한다. 다중 모드 정류기는 입력 전압의 크기에 따라 자동으로 전파 정류기, 1단 전압 체배기, 2단 전압 체배기로 동작한다. 일반적인 전파 정류기는 10 V에서 20 V까지의 입력 AC 전압에 대해 9 V에서 19 V까지의 출력 DC 전압을 생성할 수 있다. 다중 모드 정류기는 전파 정류기 보다 입력 범위를 5 V 향상시켜서 5 V에서 20 V까지의 입력 AC 전압에 대해 출력 DC 전압은 7.5 V에서 19 V까지 생성되는 것을 보여준다. 다중 모드 정류기의 효율은 전파 정류기 모드에서 94%이다. 제안하는 다중 모드 정류기는 0.35${\mu}m$ BCD 공정으로 설계되었고, 면적은 $2500{\mu}m{\times}1750{\mu}m$ 이다.

• Journal of Periodontal and Implant Science
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• 제39권4호
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• pp.385-390
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• 2009

Purpose: In this study we evaluated the morphologic aspects of defects created by a piezoelectric ultrasonic scaler with scaler tip on casting gold alloy using scanning electron microscope (SEM) images and defect surface profiles. Methods: 54 blocks of type III casting gold alloy (Firmilay, Jellenko Inc, CA, USA) were scaled by a piezoelectric ultrasonic scaler (P-MAX, Satelec, France) with scaler tip (No. 1 tip) on a sledge device. 2-dimensional profiles of defects on all samples were investigated by a surface profilometer (a-Step 500, KLA-Tencor, CA, USA). The selected working parameters were lateral force (0.5 N, 1.0 N, 2.0 N), mode (P mode, S mode), and power setting (2, 4, 8). SEM images were obtained. Defect surface profiles were made on Microsoft Excel program using data obtained by a surface profilometer. Results: Among P mode samples, there were similarities on defect surface profiles and SEM images regardless of lateral force. The defects created in P mode were narrow and shallow although the depth and the width increased as power setting changed low (2) to high (8). In P mode samples, the defect depth was the greatest when lateral force of 0.5 N was applied. However all the depths were smaller than 1 m. SEM images of Lateral force of 0.5 N, S mode, power setting 2 and 4 were similar to that of P mode, but the other SEM images of S mode showed discernible changes. Defect depth of S mode samples was the greatest when lateral force of 1.0 N was applied. Conclusions: Within the limitations of this study, it can be concoluded that removing capability of piezoelectric scaler with scaler tip becomes maximized as power level becomes higher but the capability is restricted when excessive lateral force is applied on scaler tip.

• 전기학회논문지
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• 제65권4호
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• pp.593-600
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• 2016

The solar array regulator for low earth orbit satellites controls a operating point of solar array for suppling electric power to the battery and the other units. Because the control object is reversed, the new approach for large and small signal analysis is needed despite using buck-converter for power stage. In this paper, the steady state analysis of solar array regulator is performed in continuous conduction mode and discontinuous conduction mode, and the border condition for each mode is established. Also, the small signal model of solar array regulator is established in discontinuous conduction mode. Experiments are carried on in worst condition which the solar array regulator can face with discontinuous conduction mode. The results show that the solar array regulator is in stable.

• 대한전자공학회논문지SD
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• 제46권2호
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• pp.45-49
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• 2009

본 논문에서는 900Mhz 대역의 UHF RFID에서 직접변환방식의 LNA/Mixer를 설계하였다. 설계된 회로는 3.3V로 동작하며, 0.18um CMOS 공정으로 구현되었다. 본 논문은 높은 self jamming 신호를 극복하기 위해 공통게이트 입력 구조를 사용하였으며, 고이득, 저이득의 두 가지 동작 모드를 갖도록 설계되었다 측정결과, 설계된 LNA/Mixer는 고이득 모드와 저이득 모드에서 각각 4dBm과 11dBm의 입력 p1dB를 갖고, 12dB와 3dB의 변환이득을 갖는다. 또한, 두 가지 모드에서 각각 60mW와 79mW의 전력을 소비하며, 16dB와 20dB의 잡음지수를 갖는다.

• 전자공학회논문지C
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• 제34C권6호
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• pp.37-43
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• 1997

In this paper, an analog-domain powr-reduction technique for a low-voltage CMOS operational amplifier and its application to clock-based VLSI systems are proposed. The proposed technique cuts off the bias current of the op amp during a half cycle of the clock in the sleeping mode and resumes the curent supply sequentially during the remaining cycle of the clock in the normal operating mode. The proposed sequential sbiasing technique reduces about 50% of the op amp power and improves the circuit performance through high phase margin and stable settling behavior of the output voltage. The power-reduction technique is applied to a sample-and-hold amplifier which is one of the critical circuit blocks used in the front-end stage of analog and/or digital integrated systems. The SHA was simulated and analyzed in a 0.8.mu.m n-well double-poly double-metal CMOS technology.

• Journal of Power Electronics
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• 제15권4호
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• pp.1026-1034
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• 2015

In this paper, a unified control strategy using the current space vector modulation (CSVM) technique is proposed and applied to a bidirectional three-phase DC/AC converter. The operation of the converter changes with the direction of the power flow. In the charging mode, it works as a buck type rectifier; and during the discharging mode, it operates as a boost type inverter, which makes it suitable as an interface between high voltage AC grids and low voltage energy storage devices. This topology has the following advantages: high conversion efficiency, high power factor at the grid side, tight control of the charging current and fast transition between the charging and discharging modes. The operating principle of the mode analysis, the gate signal generation, the general control strategy and the transition from a constant current (CC) to a constant voltage (CV) in the charging mode are discussed. The proposed control strategy has been validated by simulations and experimental results obtained with a 1kW laboratory prototype using supercapacitors as an energy storage device.