• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.8
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• pp.959-965
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• 2019

In this paper, we design a low noise amplifier to support ka-band satellite communication systems using 65-nm RFCMOS process. The proposed low noise amplifier is designed with high-gain mode and low-gain mode, and is designed to control the gain according to the magnitude of the input signal. In order to reduce the power consumption, the supply voltage of the entire circuit is limited to 1 V or less. We proposed the gain control circuit that consists of the inverter structure. The 3D EM simulator is used to reduce the size of the circuit. The size of the designed amplifier including pad is $0.33mm^2$. The fabricated amplifier has a -7 dB gain control range in 3 dB bandwidth and the reflection coefficient is less than -6 dB in high gain mode and less than -15 dB in low gain mode.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.1-7
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• 2016

In this paper, the tunable filter based on high power cavity using mechanical switch for 1.5 GHz band is presented. The LPF is inserted to eliminate the spurious wave, coupler is embeded to extract the output power, and then the tunable filter system is configured using mechanical switch. The LPF obtains attenuation over 40 dB between 4 GHz and 12.75 GHz, Coupler is satisfied with coupling value 40 dB and coupling isolation over 55 dB. The tunable filter system using mechanical switch obtains insertion loss 0.88 dB at bypass mode between 1,495.9 MHz and 1,510. 9 MHz, 3.29 dB at fil mode between 1,495.9 MHz and 1,500.9 MHz. It is also satisfied with output power of 132 W at the center frequency 1,498.4 MHz, and switching time below 10 ms.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2024-2034
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• 2016

This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 MHz and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a $0.18{\mu}m$ BCD process, and the die area is $3.96mm^2$. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

• The Transactions of the Korean Institute of Power Electronics
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• v.11 no.6
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• pp.535-542
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• 2006

A large signal stability analysis of the solar array regulator system is performed to facilitate the design and analysis of a Low-Earth-Orbit satellite power system. The effective load characteristics of every controllable method in the solar array system are classified to analyze the large signal stability. Then, using the state plane analysis technique, the stability of various equilibrium points is analyzed. A nonlinear transformation algorithm, which changes the effective load characteristic of the solar array regulator as constant resistive load, is also proposed for the large signal stability. The proposed resistive current mode control system can control the solar array output for purposes such as peak power tracking control and battery charging control. For the verification of the proposed large signal analysis and resistive current mode control, a solar array regulator system consisting of two 100W parallel module buck converters has been built and tested using a real 200W solar array.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.89-95
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• 2008

In this paper, we designed a low power face detection hardware and analysed its power consumption. The face detection hardware was fabricated using Samsung 0.18um CMOS technology and it can detect multiple face locations from a 2-D image. The hardware is composed of 6 functional modules and 11 internal memories. We introduced two operating modes(SLEEP and ACTIVE) to save power and a clock gating technique was used at two different levels: modules and registers. In additional, we divided an internal memory into several pieces to reduce the energy consumed when accessing memories, and fully utilized low power design option provided in Synopsis Design Compiler. As a result, we could obtain 68% power reduction in ACTIVE mode compared to the original design in which none of the above low power techniques were used.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.149-152
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• 2000

A dual-mode multiplier (DMM) that performs single- and double-precision multiplications has been designed. An algorithm for efficiently implementing double-precision multiplication with a single-precision multiplier was proposed, which is based on partitioning double-precision multiplication into four single-precision sub-multiplications and computing them with sequential accumulations. When compared with conventional double-precision multipliers, our approach reduces the hardware complexity by about one third resulting in small silicon area and low-power dissipation at the expense of increased latency and throughput cycles.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.200-201
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• 2013

This paper investigates a new approach for Li-Ion battery state-of-charge (SOC) estimation using sliding mode observer (SMO) technique including parameters aging compensation via recursive least squares (RLS). The main advantages of this approach would be low computational load, easiness of implementation along with the robustness of the method for internal battery model parameters estimation. The proposed algorithm was first tested on a set of acquired battery data using implementation in Simulink and later developed as C-code module for firmware application.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.818-823
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• 1998

A three-arm PWM UPS is realizable low price and small size UPS. In this UPS configuration, the center arm operates in both PWM converter mode and PWM inverter mode. Therefore, the operation of this UPS differs from the conventional UPS. In this paper, the three-arm PWM UPS is analyzed and a trial product is realized.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1035-1037
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• 1992

Generally, fuel cell has characteristics of low voltage, large current and voltage variation under load change. Therefore, DC output voltage of fuel cell is too low to convert into AC with high efficiency and good performance. For this reason, fuel cell generating system is composed of DC-DC converter and inverter in cascade. This paper used 2-phase boost DC-DC converter to obtain low distortion waveform and reduce input-output current ripple, and discussed inverter which can be operated in independent drive mode and utility line interface drive mode. Then, the change of modes can be achived smoothly.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2004.05a
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• pp.1047-1051
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• 2004

Charge amplifier systems benefit from the very wide dynamic range of PE accelerometers by offering flexibility in adjusting the electrical output characteristics such as sensitivity and range. They are well suited for operation at high temperatures. Modern charge systems feature improved low noise operation, simplified digital controls, and dual mode operation for operation with charge or IEPE voltage mode sensors. high impedance circuitry is not well suited for operation in adverse field or factory environments. The resolution of a PE accelerometer may not be specified or known since noise is a system consideration determined by cable length and amplifier gain. IEPE accelerometrs operate from a constant current power source, provide a high-voltage, low-impedance, fixed mV/g output. They operate through long, ordinary, coaxial cable in adverse environments without degradation of signal quality. They have limited high temperature range. IEPE sensors are simple to operate. Both resolution and operating range are defined specifications. Cost perchannel is lower compared to PE systems since low-noise cable and charge amplifiers are not required.