• Journal of Sensor Science and Technology
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• v.26 no.4
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• pp.292-296
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• 2017

It has become ever harder to design reliable circuits with each nanometer technology node under normal operation conditions, a transistor device can be affected by various aging effects resulting in performance degradation and eventually design failure. The reliability (aging) effect has traditionally been the area of process engineers. However, in the future, even the smallest of variations can slow down a transistor's switching speed, and an aging device may not perform adequately at a very low voltage. Because of such dilemmas, the transistor aging is emerging as a circuit designer's problem. Therefore, in this paper, the impact of aging effects on the delay and power dissipation of digital circuits by using nanomneter MOSFET power gating structure has been analyzed.. Based on this analyzed aging models, a reliable digital circuits can be designed.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.12
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• pp.1021-1026
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• 2002

As the development of semiconductor process technology continue to advance, ICs continue their trend toward higher performance low power system-on-chip (SOC). These circuits require on board multi power supply. In this paper, a 0.5 ㎛ dual date oxide CMOS Process technology for multi-power application is demonstrated. 5 V and 20 V devices fabricated by proposed process is measured. From 5 V devices using dual gate precess, we got almost the same characteristics as are obtained from standard 5 V devices. And the characteristics of the 20 V device demonstrates that 3 ㎛ devices with minimum gate length are available without reliability degradation. Electrical parameters in minimum 3 ㎛ devices are 520 ㎂/㎛ current density, 120 ㎷ DIBL, 24 V BV for NMOS and ,350 ㎂/㎛ current density, 180 ㎷ DIBL, 26 V BV for PMOS, respectively.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.439-442
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• 2002

We present in this Paper a microwave Power sensor fabricated by a standard CMOS process and a bulk micromachining process. The sensor consists of a CPW transmission line, a resistor as a healer, and thermocouple arrays. An input microwave heater, the resistor so that the temperature rises proportionally to the microwave power and tile thermocouple arrays convert it to an electrical signal. The sensor uses air bridged 8round of CPW realized by wire bonding to reduce tile device size and cost and to improve the thermal impedance. Al/poly-Si junctions are used for the thermocouples. Poly-Si is used for tile resister and Aluminium is for transmission line. The resistor and hot junctions of the thermocouples are placed on a low stress silicon nitride diaphragm to minimize a thermal loss. The fabricated device operates properly from 1㎼ to 100㎽\ulcorner of input power. The sensitivity was measured to be ,3.2～4.7 V/W.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.365-368
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• 2004

Charge compensation effects in multi-resurf structure make possible to obtain high breakdown volatage and low on-resistance in vertical MOSFET. In this paper, electrical characteristics of the vertical MOSFET with multi epitaxial layer is presented. Proposed device has n and p-pillar for obtaining the charge compensation effects and The doping concentration each pillar is varied from $5{\times}10^{14}\;to\;1{\times}10^{16}/cm^3$. The thickness of the proposed device also varied from $400{\mu}m\;to\;500{\mu}m$. Due to the charge compensation effects, 4500V of breakdown voltage can be obtained.

• Journal of IKEEE
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• v.12 no.2
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• pp.110-117
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• 2008

This paper presents a new Insulated Gate Bipolar Transistor(IGBT) based on Non Punch Through(NPT) IGBT structure for power switching device. The proposed structure has adding N+ beside the P-base region of the conventional IGBT structure. The added n+ diffusion of the proposed device ensure device has faster turn-off time and lower forward conduction loss than the conventional IGBT structure. But, added n+ region can reduce th breakdown voltage and latching current density of the proposed device due to its high doping concentration. This problems can be overcome by using diverter on the right side of the device. In the simulation results, turn-off time of the proposed device is 0.3us and the on-state voltage drop is 3V. The results show that the proposed device has superior characteristic than conventional structure.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.9
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• pp.1626-1631
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• 2016

Generally, the low-voltage customer has been used with a linear load and nonlinear load in the 3-phase 4-wire distribution system. Linear load has usually configured the resistance and inductance, current phase is slower than the voltage phase, so power factor is low. It is required for the power factor correction device prior to the phase of the current than the voltage. The capacitor is connected in parallel to the load in order to ensure a low power factor. Power converter such as an inverter is a typical non-linear load. Non-linear load generates harmonic currents in the energy conversion process. Many electrical equipment may be adversely affected by the harmonic current. There, passive or active filter have been used to reduce these harmonics current. Passive filter consisting of inductor and capacitor generates a reactive power. According to the combination of filter inductor and capacitor, reactive power can be adjusted. In this paper, we analyzed how the combination of inductor and capacitor affects the overall power factor by simulation and measurement.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.1
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• pp.51-56
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• 1999

This paper presents a new transient overvoltage blocking device (TOBD) for info-communication facilities with low power and high frequency bandwidth. Conventional protection devices have some problems such as low frequency bandwidth, low energy capacity and high remnant voltage. In order to improve these limitations, thehybrid type TOBD, which consists of a gas tube, avalanche diodes and junction typefield effect transistors (JFETs), was designed and fabricated. The TOBD differs from the conventional protection devices in configuration, and JFETs were used as an active non-linear element and a high speed switching diode with low capacitance limits high current. Therefore the avalanche dilde with low energy capacity are protected fromthe high current, and the TOBD has a very small input capacitance. From the performance test using combination surge generator, which can produce $1.2/50\mus\;4.2kV_{max}\; 8/20\mus\; 2.1kA_{max}$, it is confirmed that proposed TOBD has an excellent protection performance in tight clamping voltage and limiting current characteristics.

• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.295-298
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• 2016

Future logic device over the FinFET generation requires a complete electrostatics and transport characteristic for low-power and high-speed operation as extremely scaled devices. Silicon, Germanium and III-V based nanowire-based MOSFET devices and few-layer TMDC (Transition metal dichalcogenide monolayers) based multi-gate devices have been brought attention from device engineers due to those excellent electrostatic and novel device characteristic. In this study, we simulated ultrascaled Si/Ge/InAs gate-all-around nanowire MOSFET and MoS2 TMDC based DG MOSFET and TFET device by tight-binding NEGF method. As a result, we can find promising candidates of the future logic device of each channel material and device structures.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.382-390
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• 2017

In this paper, we consider particular exposure scenarios to evaluate human effects for inductive commercial wireless charging device operating at low frequency. The coil used in this study is the A10 model in Qi standard proposed by WPC(Wireless Power Consortium), and input power is 5 W to the operating frequency of 155 kHz. In perfectly aligned condition, the max leakage magnetic field is $257.58{\mu}T$ which is obtained at the side of the device, and it is exceeded about 7.4 times of the ICNIRP 1998 reference level. The SAR is evaluated with homogeneous phantom which has electric constants of wet skin. The max value of the SAR is $134.47{\mu}W/kg$ which is obtained at the side of the device also, and it is much lower than the international guidelines. Especially, it showed higher SAR values in case of misalignment condition, so we will need to consider the misalignment condition importantly when we evaluate human effects for wireless power transfer system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.50-55
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• 2008

As more DSP functionalities are integrated into an embedded mobile device, power consumption and device reliability have emerged as crucial issues. As the complexity of mobile embedded designs increases very rapidly, verifying the functionality of the mobile devices has become extremely difficult. Therefore, designs with error (fault) tolerance are often required since these capabilities will enable the design to operate properly even with some existence of errors. However, designs with fault tolerance may suffer from significant power overhead since fault tolerance is often achieved by resource replication. In this paper, we propose a low power and fault tolerant MAC (multiply-and-accumulate) design. The proposed MAC design is based on multiple barrel shifters since MAC designs with barrel-shifters and adders are known to be excellent in terms of power consumption.