• Title/Summary/Keyword: low power density

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Electrical Characteristics of SiO2/4H-SiC Metal-oxide-semiconductor Capacitors with Low-temperature Atomic Layer Deposited SiO2

  • Jo, Yoo Jin;Moon, Jeong Hyun;Seok, Ogyun;Bahng, Wook;Park, Tae Joo;Ha, Min-Woo
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.2
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    • pp.265-270
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    • 2017
  • 4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.

Fatigue Strength Analysis of Propulsion Shafting System with Two Stroke Low Speed Diesel Engine by Torsional Vibration in Frequency Domain (주파수 영역에서 비틀림진동에 의한 저속 2행정 디젤엔진을 갖는 추진축계의 피로강도 해석)

  • Kim, S.H.;Lee, D.C.
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2007.05a
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    • pp.416-422
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    • 2007
  • Prime movers in most large merchant ships adapt two stroke low speed diesel engine which has higher efficiency, mobility and durability. However, severe torsional vibration in these diesel engines may be induced by higher fluctuation of combustion pressures. Consequently, it may lead sometimes to propulsion shafting failure due to the accumulated fatigue stresses. Shaft fatigue strength analysis had been done traditionally in time domain but this method is complicated and difficult in analysing bi-modal vibration system such as the case of cylinder misfiring condition. In this paper authors introduce an assessment method of fatigue strength estimation for propulsion shafting system with two stroke low speed diesel engine in the frequency domain.

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Design and Analysis of Axial Flux Permanent Magnet Synchronous Machine

  • Jo, Won-Young;Lee, In-Jae;Cho, Yun-Hyun;Koo, Dae-Hyun;Chun, Yon-Do
    • Journal of Electrical Engineering and Technology
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    • v.2 no.1
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    • pp.61-67
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    • 2007
  • In this article, a special kind of axial flux permanent magnet machine has proved to be suitable for high torque and low speed applications. An innovative design of the machine has been proposed in order to make the machine suitable for traction applications by means of field-weakening. The aim of this paper is to analyze, in general terms, the basic equations that describe the operating conditions of such machines. Optimal sizes for design can be obtained by calculating the power density and the air-gap flux density, etc.

Sensing Parameter Selection Strategy for Ultra-low-power Micro-servosystem Identification (초저전력 마이크로 서보시스템의 모델식별을 위한 계측 파라미터 선정 기법)

  • Hahn, Bongsu
    • Journal of Institute of Control, Robotics and Systems
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    • v.20 no.8
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    • pp.849-853
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    • 2014
  • In micro-scale electromechanical systems, the power to perform accurate position sensing often greatly exceeds the power needed to generate motion. This paper explores the implications of sampling rate and amplifier noise density selection on the performance of a system identification algorithm using a capacitive sensing circuit. Specific performance objectives are to minimize or limit convergence rate and power consumption to identify the dynamics of a rotary micro-stage. A rearrangement of the conventional recursive least-squares identification algorithm is performed to make operating cost an explicit function of sensor design parameters. It is observed that there is a strong dependence of convergence rate and error on the sampling rate, while energy dependence is driven by error that may be tolerated in the final identified parameters.

Low power high level synthesis by increasing data correlation (데이타 상관 증가에 의한 저전력 상위 수준 합성)

  • 신동완;최기영
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.5
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    • pp.1-17
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    • 1997
  • With the increasing performance and density of VLSI scircuits as well as the popularity of portable devices such as personal digital assitance, power consumption has emerged as an important issue in the design of electronic systems. Low power design techniqeus have been pursued at all design levels. However, it is more effective to attempt to reduce power dissipation at higher levels of abstraction which allow wider view. In this paper, we propose a simultaneous scheduling and binding scheme which increases the correlation between cosecutive inputs to an operation so that the switched capacitance of execution units is reduced in datapath-dominated circuits. The proposed method is implemented and integrated into the scheduling and assignment part of HYPER synthesis environment. Compared with original HYPER synthesis system, average power saving of 23.0% in execution units and 14.2% in the whole circuits, ar eobtained for a set of benchmark examples.

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A CLB based CPLD Low-power Technology Mapping Algorithm consider Area and Delay time (면적과 지연 시간을 고려한 CLB 구조의 CPLD 저전력 기술 매핑 알고리즘)

  • 김재진;조남경;전종식;김희석
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1169-1172
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    • 2003
  • In this paper, a CLB-based CPLD low-power technology mapping algorithm consider area and delay time is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. The proposed algorithm is examined by using benchmarks in SIS. In the case of that the number of OR-terms is 5, the experiments results show that reduce the power consumption by 30.73% comparing with that of TEMPLA, and 17.11% comparing with that of PLAmap respectively.

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Power Conditioning System using LLC Resonant Inverter with Two Resonant Tanks (두개의 공진탱크회로를 갖는 LLC 공진 인버터 적용 PCS)

  • Yoon, Kwang-Ho;Chung, Bong-Gun;Lee, Kwang-Ho;Kim, Joo-Hoon;Kim, Eun-Soo;Choi, Joon-Young
    • The Transactions of the Korean Institute of Power Electronics
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    • v.15 no.6
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    • pp.477-486
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    • 2010
  • Recently, Power Conditioning System (PCS) tends to become more compact, and tends to require higher efficiency, and higher power density with better performance. To meet these requirements, a novel topology consisted of LLC resonant inverter with two resonant tanks for low power losses and Low Frequency (LF) cyclo-converter for sine wave filtering is proposed. The operating schemes are analyzed and described. A 400W proto product is built, tested and verified the performances by connecting the 110Vac 60Hz utility line.

An offset-voltage reduction technique for system applications of a low-power CMOS comparator (저전력용 CMOS 비교기의 시스템 응용을 위한 옵셋 전압 최소화 기법)

  • 곽명보;이승훈;이인환
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.12
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    • pp.28-36
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    • 1997
  • In this paper, system application techniques of a low-voltage low-power CMOS comparator are proposed. The proposed techniques employ poly-layer lines instead of conventional dummy cells to improve the accuracy of comparators which are located in both ends of a comparator array. This technique is easily applicable for hihg-density systems such as memory. The proposed circuits are implemented using a 0.6 um signle-poly double-metal n-well CMOS technology and the dissipated power is 0.38 mW. at a 20MHz clock speed based on a 3V supply. The comparator offsets are measured separately and compared for system applications. Using the proposed techniues, the measured comparator offsets are reduced by 40% of a conventional case.

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Analysis of Key Parameters for Inductively Coupled Power Transfer Systems Realized by Detuning Factor in Synchronous Generators

  • Liu, Jinfeng;Li, Kun;Jin, Ningzhi;Iu, Herbert Ho-Ching
    • Journal of Power Electronics
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    • v.19 no.5
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    • pp.1087-1098
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    • 2019
  • In this paper, a detuning factor (DeFac) method is proposed to design the key parameters for optimizing the transfer power and efficiency of an Inductively Coupled Power Transfer (ICPT) system with primary-secondary side compensation. Depending on the robustness of the system, the DeFac method can guarantee the stability of the transfer power and efficiency of an ICPT system within a certain range of resistive-capacitive or resistive-inductive loads. A MATLAB-Simulink model of a ICPT system was built to assess the system's main evaluation criteria, namely its maximum power ratio (PR) and efficiency, in terms of different approaches. In addition, a magnetic field simulation model was built using Ansoft to specify the leakage flux and current density. Simulation results show that both the maximum PR and efficiency of the ICPT system can reach almost 70% despite the severe detuning imposed by the DeFac method. The system also exhibited low levels of leakage flux and a high current density. Experimental results confirmed the validity and feasibility of an ICPT system using DeFac-designed parameters.

Spectral Analysis of Heart Rate Variability in ECG and Pulse-wave using autoregressive model (AR모델을 이용한 심전도와 맥파의 심박변동 스펙트럼 해석)

  • Kim NagHwan;Lee EunSil;Min HongKi;Lee EungHyuk;Hong SeungHong
    • Journal of the Institute of Convergence Signal Processing
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    • v.1 no.1
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    • pp.15-22
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    • 2000
  • The analysis of power spectrum based on linear AR model is applied widely to quantize the response of autonomic nerve noninvasively, In this paper, we estimate the power spectrum density for heartrate variability of the electrocadiogram and pulse wave for short term data(less than two minute), The time series of heart rate variability is obtained from the time interval(RRI, PPI) between the feature point of the electrocadiogram and pulse wave for normal person, The generated time series reconstructed into new time series through polynomial interpolation to apply to the AR mode. The power spectrum density for AR model is calculated by Burg algorithm, After applying AR model, the power spectrum density for heart rate variability of the electrocadiogram and the pulse wave is shown smooth spectrum power at the region of low frequence and high frequence, and that the power spectrum density of electrocadiogram and pulse wave has similar form for same subject.

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